testbench Architecture Reference

Processes
stim_proc	( )

Components
top_ftm_dss	<Entity top_ftm_dss>

Constants
clock_period	time := 25 ns

Signals
sysclk_p	std_logic := ' 0 '
sysclk_n	std_logic := ' 0 '
fpga_number	std_logic := ' 0 '
slave_rx_data_p	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
slave_rx_data_n	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
slave_rx_parity_p	std_logic := ' 0 '
slave_rx_parity_n	std_logic := ' 0 '
slave_tx_pause_p	std_logic := ' 0 '
slave_tx_pause_n	std_logic := ' 0 '
slave_tx_data_p	std_logic_vector ( 8 downto 0 )
slave_tx_data_n	std_logic_vector ( 8 downto 0 )
slave_tx_parity_p	std_logic
slave_tx_parity_n	std_logic
config_csn	std_logic
config_mosi	std_logic
config_miso	std_logic := ' 0 '
locked	std_logic
test_clk	std_logic
got_ip_addr	std_logic
onehz	std_logic

Instantiations
uut	top_ftm_dss <Entity top_ftm_dss>

Member Function Documentation

stim_proc()

stim_proc

(

)

Member Data Documentation

clock_period

clock_period time := 25 ns

Constant

config_csn

config_csn std_logic

Signal

config_miso

config_miso std_logic := ' 0 '

Signal

config_mosi

config_mosi std_logic

Signal

fpga_number

fpga_number std_logic := ' 0 '

Signal

got_ip_addr

got_ip_addr std_logic

Signal

locked

locked std_logic

Signal

onehz

onehz std_logic

Signal

slave_rx_data_n

slave_rx_data_n std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )

Signal

slave_rx_data_p

slave_rx_data_p std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )

Signal

slave_rx_parity_n

slave_rx_parity_n std_logic := ' 0 '

Signal

slave_rx_parity_p

slave_rx_parity_p std_logic := ' 0 '

Signal

slave_tx_data_n

slave_tx_data_n std_logic_vector ( 8 downto 0 )

Signal

slave_tx_data_p

slave_tx_data_p std_logic_vector ( 8 downto 0 )

Signal

slave_tx_parity_n

slave_tx_parity_n std_logic

Signal

slave_tx_parity_p

slave_tx_parity_p std_logic

Signal

slave_tx_pause_n

slave_tx_pause_n std_logic := ' 0 '

Signal

slave_tx_pause_p

slave_tx_pause_p std_logic := ' 0 '

Signal

sysclk_n

sysclk_n std_logic := ' 0 '

Signal

sysclk_p

sysclk_p std_logic := ' 0 '

Signal

test_clk

test_clk std_logic

Signal

top_ftm_dss

top_ftm_dss

Component

uut

uut top_ftm_dss

Instantiation

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The documentation for this class was generated from the following file:

• testbench/ftm_dss_tb.vhd