top_ftm_dss Entity Reference

Inheritance diagram for top_ftm_dss:

Collaboration diagram for top_ftm_dss:

Entities
rtl	architecture

Libraries
IEEE
unisim

Use Clauses
STD_LOGIC_1164
VComponents
ipbus	Package <ipbus>
spi	Package <spi>
ftm	Package <ftm>

Ports
sysclk_p	in STD_LOGIC
sysclk_n	in STD_LOGIC
ttc_clk_p	in STD_LOGIC
ttc_clk_n	in STD_LOGIC
GTREFCLK1_P	in std_logic
GTREFCLK1_N	in std_logic
RXP_I	in std_logic_vector ( 11 DOWNTO 0 )
RXN_I	in std_logic_vector ( 11 DOWNTO 0 )
TXP_O	out std_logic_vector ( 11 DOWNTO 0 )
TXN_O	out std_logic_vector ( 11 DOWNTO 0 )
GTREFCLK0P_I	in std_logic_vector ( 2 DOWNTO 0 )
GTREFCLK0N_I	in std_logic_vector ( 2 DOWNTO 0 )
GTREFCLK1P_I	in std_logic_vector ( 2 DOWNTO 0 )
GTREFCLK1N_I	in std_logic_vector ( 2 DOWNTO 0 )
fpga_number	in STD_LOGIC
slave_rx_data_p	in std_logic_vector ( 8 DOWNTO 0 )
slave_rx_data_n	in std_logic_vector ( 8 DOWNTO 0 )
slave_rx_parity_p	in std_logic
slave_rx_parity_n	in std_logic
slave_tx_pause_p	in std_logic
slave_tx_pause_n	in std_logic
slave_tx_data_p	out std_logic_vector ( 8 DOWNTO 0 )
slave_tx_data_n	out std_logic_vector ( 8 DOWNTO 0 )
slave_tx_parity_p	out std_logic
slave_tx_parity_n	out std_logic
dss_reset	in STD_LOGIC
test_pin2	out STD_LOGIC
ttc_sync_p	in std_logic
ttc_sync_n	in std_logic
ttc_spin_p	in std_logic
ttc_spin_n	in std_logic
config_csn	out STD_LOGIC
config_mosi	out STD_LOGIC
config_miso	in STD_LOGIC
locked	out STD_LOGIC
got_ip_addr	out std_logic
onehz	out STD_LOGIC

Member Data Documentation

config_csn

config_csn out STD_LOGIC

Port

config_miso

config_miso in STD_LOGIC

Port

config_mosi

config_mosi out STD_LOGIC

Port

dss_reset

dss_reset in STD_LOGIC

Port

fpga_number

fpga_number in STD_LOGIC

Port

ftm

ftm

Package

got_ip_addr

got_ip_addr out std_logic

Port

GTREFCLK0N_I

GTREFCLK0N_I in std_logic_vector ( 2 DOWNTO 0 )

Port

GTREFCLK0P_I

GTREFCLK0P_I in std_logic_vector ( 2 DOWNTO 0 )

Port

GTREFCLK1_N

GTREFCLK1_N in std_logic

Port

GTREFCLK1_P

GTREFCLK1_P in std_logic

Port

GTREFCLK1N_I

GTREFCLK1N_I in std_logic_vector ( 2 DOWNTO 0 )

Port

GTREFCLK1P_I

GTREFCLK1P_I in std_logic_vector ( 2 DOWNTO 0 )

Port

IEEE

IEEE

Library

ipbus

ipbus

Package

locked

locked out STD_LOGIC

Port

onehz

onehz out STD_LOGIC

Port

RXN_I

RXN_I in std_logic_vector ( 11 DOWNTO 0 )

Port

RXP_I

RXP_I in std_logic_vector ( 11 DOWNTO 0 )

Port

slave_rx_data_n

slave_rx_data_n in std_logic_vector ( 8 DOWNTO 0 )

Port

slave_rx_data_p

slave_rx_data_p in std_logic_vector ( 8 DOWNTO 0 )

Port

slave_rx_parity_n

slave_rx_parity_n in std_logic

Port

slave_rx_parity_p

slave_rx_parity_p in std_logic

Port

slave_tx_data_n

slave_tx_data_n out std_logic_vector ( 8 DOWNTO 0 )

Port

slave_tx_data_p

slave_tx_data_p out std_logic_vector ( 8 DOWNTO 0 )

Port

slave_tx_parity_n

slave_tx_parity_n out std_logic

Port

slave_tx_parity_p

slave_tx_parity_p out std_logic

Port

slave_tx_pause_n

slave_tx_pause_n in std_logic

Port

slave_tx_pause_p

slave_tx_pause_p in std_logic

Port

spi

spi

Package

STD_LOGIC_1164

STD_LOGIC_1164

Package

sysclk_n

sysclk_n in STD_LOGIC

Port

sysclk_p

sysclk_p in STD_LOGIC

Port

test_pin2

test_pin2 out STD_LOGIC

Port

ttc_clk_n

ttc_clk_n in STD_LOGIC

Port

ttc_clk_p

ttc_clk_p in STD_LOGIC

Port

ttc_spin_n

ttc_spin_n in std_logic

Port

ttc_spin_p

ttc_spin_p in std_logic

Port

ttc_sync_n

ttc_sync_n in std_logic

Port

ttc_sync_p

ttc_sync_p in std_logic

Port

TXN_O

TXN_O out std_logic_vector ( 11 DOWNTO 0 )

Port

TXP_O

TXP_O out std_logic_vector ( 11 DOWNTO 0 )

Port

unisim

unisim

Library

VComponents

VComponents

Package

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The documentation for this class was generated from the following file:

• FTM/DSS/hdl/top_ftm_dss_ibert.vhd