rtl Architecture Reference

Processes
PROCESS_442	( clk125 )

Components
ibert_V7_114_116

Signals
slave_tx_data	std_logic_vector ( 8 DOWNTO 0 )
slave_tx_data_reg	std_logic_vector ( 8 DOWNTO 0 )
slave_rx_data	std_logic_vector ( 8 DOWNTO 0 )
slave_rx_data_reg	std_logic_vector ( 8 DOWNTO 0 )
slave_rx_err	std_logic
slave_tx_pause	std_logic
slave_tx_parity	std_logic
slave_tx_parity_reg	std_logic
slave_rx_parity	std_logic
slave_rx_parity_reg	std_logic
slave_rx_parity_chk	std_logic_vector ( 9 DOWNTO 0 )
clk125	STD_LOGIC
ipb_clk	STD_LOGIC
rst_125	STD_LOGIC
rst_ipb	STD_LOGIC
mac_tx_data	std_logic_vector ( 7 downto 0 )
mac_rx_data	std_logic_vector ( 7 downto 0 )
mac_tx_valid	std_logic
mac_tx_last	std_logic
mac_tx_error	std_logic
mac_tx_ready	std_logic
mac_rx_valid	std_logic
mac_rx_last	std_logic
mac_rx_error	std_logic
ipb_master_out	ipb_wbus
ipb_master_in	ipb_rbus
mac_addr	std_logic_vector ( 47 downto 0 )
ip_addr	std_logic_vector ( 31 downto 0 )
sys_rst	std_logic
flash_o_int	spi_mo
flash_i_int	spi_mi
sync	std_logic := ' 0 '
spin	std_logic := ' 0 '
mgt_clk	std_logic := ' 0 '
gtrefclk	std_logic := ' 0 '
ttc_40Mclk	std_logic
IPBus_port_default	std_logic_vector ( 15 downto 0 ) := x " C352 "
IPBus_port_this	std_logic_vector ( 15 downto 0 )
Remote_Got_IP_addr	std_logic
gtrefclk0_i	std_logic_vector ( 2 DOWNTO 0 )
gtrefclk1_i	std_logic_vector ( 2 DOWNTO 0 )
refclk0_i	std_logic_vector ( 2 DOWNTO 0 )
refclk1_i	std_logic_vector ( 2 DOWNTO 0 )
sysclk_i	std_logic

Instantiations
ibuf_40m	ibufgds
gen_clock_as_data	clock_pulse <Entity clock_pulse>
bufg_mgt	bufg
u_buf_q12_clk0	ibufds_gte2
u_buf_q12_clk1	ibufds_gte2
u_buf_q13_clk0	ibufds_gte2
u_buf_q13_clk1	ibufds_gte2
u_buf_q14_clk0	ibufds_gte2
u_buf_q14_clk1	ibufds_gte2
u_ibert_core	ibert_v7_114_116
clocks	clocks_7s_extphy <Entity clocks_7s_extphy>
s2m	obufds
s2mp	obufds
m2s	ibufds
m2s_err	ibufds
m2s_pause	ibufds
interconnect_slave	UDP_slave_if <Entity UDP_slave_if>
ipbus	ipbus_ctrl <Entity ipbus_ctrl>
ttc_info_spin	ibufds
ttc_info_sync	ibufds
slaves	slaves <Entity slaves>
cclk_o	startup <Entity startup>

Member Function Documentation

PROCESS_442()

PROCESS_442

(

clk125

)

Member Data Documentation

bufg_mgt

bufg_mgt bufg

Instantiation

cclk_o

cclk_o startup

Instantiation

clk125

clk125 STD_LOGIC

Signal

clocks

clocks clocks_7s_extphy

Instantiation

flash_i_int

flash_i_int spi_mi

Signal

flash_o_int

flash_o_int spi_mo

Signal

gen_clock_as_data

gen_clock_as_data clock_pulse

Instantiation

gtrefclk

gtrefclk std_logic := ' 0 '

Signal

gtrefclk0_i

gtrefclk0_i std_logic_vector ( 2 DOWNTO 0 )

Signal

gtrefclk1_i

gtrefclk1_i std_logic_vector ( 2 DOWNTO 0 )

Signal

ibert_V7_114_116

ibert_V7_114_116

Component

ibuf_40m

ibuf_40m ibufgds

Instantiation

interconnect_slave

interconnect_slave UDP_slave_if

Instantiation

ip_addr

ip_addr std_logic_vector ( 31 downto 0 )

Signal

ipb_clk

ipb_clk STD_LOGIC

Signal

ipb_master_in

ipb_master_in ipb_rbus

Signal

ipb_master_out

ipb_master_out ipb_wbus

Signal

ipbus

ipbus ipbus_ctrl

Instantiation

IPBus_port_default

IPBus_port_default std_logic_vector ( 15 downto 0 ) := x " C352 "

Signal

IPBus_port_this

IPBus_port_this std_logic_vector ( 15 downto 0 )

Signal

m2s

m2s ibufds

Instantiation

m2s_err

m2s_err ibufds

Instantiation

m2s_pause

m2s_pause ibufds

Instantiation

mac_addr

mac_addr std_logic_vector ( 47 downto 0 )

Signal

mac_rx_data

mac_rx_data std_logic_vector ( 7 downto 0 )

Signal

mac_rx_error

mac_rx_error std_logic

Signal

mac_rx_last

mac_rx_last std_logic

Signal

mac_rx_valid

mac_rx_valid std_logic

Signal

mac_tx_data

mac_tx_data std_logic_vector ( 7 downto 0 )

Signal

mac_tx_error

mac_tx_error std_logic

Signal

mac_tx_last

mac_tx_last std_logic

Signal

mac_tx_ready

mac_tx_ready std_logic

Signal

mac_tx_valid

mac_tx_valid std_logic

Signal

mgt_clk

mgt_clk std_logic := ' 0 '

Signal

refclk0_i

refclk0_i std_logic_vector ( 2 DOWNTO 0 )

Signal

refclk1_i

refclk1_i std_logic_vector ( 2 DOWNTO 0 )

Signal

Remote_Got_IP_addr

Remote_Got_IP_addr std_logic

Signal

rst_125

rst_125 STD_LOGIC

Signal

rst_ipb

rst_ipb STD_LOGIC

Signal

s2m

s2m obufds

Instantiation

s2mp

s2mp obufds

Instantiation

slave_rx_data

slave_rx_data std_logic_vector ( 8 DOWNTO 0 )

Signal

slave_rx_data_reg

slave_rx_data_reg std_logic_vector ( 8 DOWNTO 0 )

Signal

slave_rx_err

slave_rx_err std_logic

Signal

slave_rx_parity

slave_rx_parity std_logic

Signal

slave_rx_parity_chk

slave_rx_parity_chk std_logic_vector ( 9 DOWNTO 0 )

Signal

slave_rx_parity_reg

slave_rx_parity_reg std_logic

Signal

slave_tx_data

slave_tx_data std_logic_vector ( 8 DOWNTO 0 )

Signal

slave_tx_data_reg

slave_tx_data_reg std_logic_vector ( 8 DOWNTO 0 )

Signal

slave_tx_parity

slave_tx_parity std_logic

Signal

slave_tx_parity_reg

slave_tx_parity_reg std_logic

Signal

slave_tx_pause

slave_tx_pause std_logic

Signal

slaves

slaves slaves

Instantiation

spin

spin std_logic := ' 0 '

Signal

sync

sync std_logic := ' 0 '

Signal

sys_rst

sys_rst std_logic

Signal

sysclk_i

sysclk_i std_logic

Signal

ttc_40Mclk

ttc_40Mclk std_logic

Signal

ttc_info_spin

ttc_info_spin ibufds

Instantiation

ttc_info_sync

ttc_info_sync ibufds

Instantiation

u_buf_q12_clk0

u_buf_q12_clk0 ibufds_gte2

Instantiation

u_buf_q12_clk1

u_buf_q12_clk1 ibufds_gte2

Instantiation

u_buf_q13_clk0

u_buf_q13_clk0 ibufds_gte2

Instantiation

u_buf_q13_clk1

u_buf_q13_clk1 ibufds_gte2

Instantiation

u_buf_q14_clk0

u_buf_q14_clk0 ibufds_gte2

Instantiation

u_buf_q14_clk1

u_buf_q14_clk1 ibufds_gte2

Instantiation

u_ibert_core

u_ibert_core ibert_v7_114_116

Instantiation

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The documentation for this class was generated from the following file:

• FTM/DSS/hdl/top_ftm_dss_ibert.vhd