gig_eth_pcs_pma_v11_5_transceiver Entity Reference

Inheritance diagram for gig_eth_pcs_pma_v11_5_transceiver:

Collaboration diagram for gig_eth_pcs_pma_v11_5_transceiver:

Entities
wrapper	architecture

Libraries
ieee
unisim

Use Clauses
std_logic_1164
numeric_std
vcomponents

Generics
EXAMPLE_SIMULATION	integer := 0

Ports
drpaddr_in	in std_logic_vector ( 8 downto 0 )
drpclk_in	in std_logic
drpdi_in	in std_logic_vector ( 15 downto 0 )
drpdo_out	out std_logic_vector ( 15 downto 0 )
drpen_in	in std_logic
drprdy_out	out std_logic
drpwe_in	in std_logic
data_valid	in std_logic
independent_clock	in std_logic
encommaalign	in std_logic
loopback	in std_logic
powerdown	in std_logic
usrclk	in std_logic
usrclk2	in std_logic
txreset	in std_logic
txdata	in std_logic_vector ( 7 downto 0 )
txchardispmode	in std_logic
txchardispval	in std_logic
txcharisk	in std_logic
rxreset	in std_logic
rxchariscomma	out std_logic
rxcharisk	out std_logic
rxclkcorcnt	out std_logic_vector ( 2 downto 0 )
rxdata	out std_logic_vector ( 7 downto 0 )
rxdisperr	out std_logic
rxnotintable	out std_logic
rxrundisp	out std_logic
rxbuferr	out std_logic
txbuferr	out std_logic
plllkdet	out std_logic
txoutclk	out std_logic
txn	out std_logic
txp	out std_logic
rxn	in std_logic
rxp	in std_logic
gtrefclk	in std_logic
pmareset	in std_logic
mmcm_locked	in std_logic
resetdone	out std_logic

Member Data Documentation

data_valid

data_valid in std_logic

Port

drpaddr_in

drpaddr_in in std_logic_vector ( 8 downto 0 )

Port

drpclk_in

drpclk_in in std_logic

Port

drpdi_in

drpdi_in in std_logic_vector ( 15 downto 0 )

Port

drpdo_out

drpdo_out out std_logic_vector ( 15 downto 0 )

Port

drpen_in

drpen_in in std_logic

Port

drprdy_out

drprdy_out out std_logic

Port

drpwe_in

drpwe_in in std_logic

Port

encommaalign

encommaalign in std_logic

Port

EXAMPLE_SIMULATION

EXAMPLE_SIMULATION integer := 0

Generic

gtrefclk

gtrefclk in std_logic

Port

ieee

ieee

Library

independent_clock

independent_clock in std_logic

Port

loopback

loopback in std_logic

Port

mmcm_locked

mmcm_locked in std_logic

Port

numeric_std

numeric_std

Package

plllkdet

plllkdet out std_logic

Port

pmareset

pmareset in std_logic

Port

powerdown

powerdown in std_logic

Port

resetdone

resetdone out std_logic

Port

rxbuferr

rxbuferr out std_logic

Port

rxchariscomma

rxchariscomma out std_logic

Port

rxcharisk

rxcharisk out std_logic

Port

rxclkcorcnt

rxclkcorcnt out std_logic_vector ( 2 downto 0 )

Port

rxdata

rxdata out std_logic_vector ( 7 downto 0 )

Port

rxdisperr

rxdisperr out std_logic

Port

rxn

rxn in std_logic

Port

rxnotintable

rxnotintable out std_logic

Port

rxp

rxp in std_logic

Port

rxreset

rxreset in std_logic

Port

rxrundisp

rxrundisp out std_logic

Port

std_logic_1164

std_logic_1164

Package

txbuferr

txbuferr out std_logic

Port

txchardispmode

txchardispmode in std_logic

Port

txchardispval

txchardispval in std_logic

Port

txcharisk

txcharisk in std_logic

Port

txdata

txdata in std_logic_vector ( 7 downto 0 )

Port

txn

txn out std_logic

Port

txoutclk

txoutclk out std_logic

Port

txp

txp out std_logic

Port

txreset

txreset in std_logic

Port

unisim

unisim

Library

usrclk

usrclk in std_logic

Port

usrclk2

usrclk2 in std_logic

Port

vcomponents

vcomponents

Package

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The documentation for this class was generated from the following files:

• components/ipbus_eth/firmware/gen_hdl/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5/example_design/transceiver/gig_eth_pcs_pma_v11_5_transceiver.vhd
• components/ipbus_eth/firmware/gen_hdl/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5_transceiver_gth.vhd
• components/ipbus_eth/firmware/gen_hdl/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5_transceiver_gtx.vhd
• components/ipbus_eth/firmware/gen_hdl/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5_transceiver_gtx_kc705.vhd