My Project  v0.0.16
Components | Signals | Processes | Instantiations
wrapper Architecture Reference

Processes

PROCESS_100  ( usrclk2 )
PROCESS_101  ( usrclk2 )
PROCESS_102  ( usrclk2 )
PROCESS_103  ( usrclk )
PROCESS_104  ( usrclk )
PROCESS_105  ( usrclk2 )
PROCESS_106  ( usrclk2 )
PROCESS_107  ( usrclk2 )
PROCESS_108  ( usrclk2 )
PROCESS_114  ( usrclk2 )
PROCESS_115  ( usrclk2 )
PROCESS_116  ( usrclk2 )
PROCESS_117  ( usrclk )
PROCESS_118  ( usrclk )
PROCESS_119  ( usrclk2 )
PROCESS_120  ( usrclk2 )
PROCESS_121  ( usrclk2 )
PROCESS_122  ( usrclk2 )
PROCESS_123  ( usrclk2 )
PROCESS_124  ( usrclk2 )
PROCESS_125  ( usrclk2 )
PROCESS_126  ( usrclk )
PROCESS_127  ( usrclk )
PROCESS_128  ( usrclk2 )
PROCESS_129  ( usrclk2 )
PROCESS_130  ( usrclk2 )
PROCESS_131  ( usrclk2 )
PROCESS_132  ( usrclk2 )
PROCESS_133  ( usrclk2 )
PROCESS_134  ( usrclk2 )
PROCESS_135  ( usrclk )
PROCESS_136  ( usrclk )
PROCESS_137  ( usrclk2 )
PROCESS_138  ( usrclk2 )
PROCESS_139  ( usrclk2 )
PROCESS_140  ( usrclk2 )
PROCESS_661  ( usrclk2 )
PROCESS_662  ( usrclk2 )
PROCESS_663  ( usrclk2 )
PROCESS_664  ( usrclk )
PROCESS_665  ( usrclk )
PROCESS_666  ( usrclk2 )
PROCESS_667  ( usrclk2 )
PROCESS_668  ( usrclk2 )
PROCESS_669  ( usrclk2 )
PROCESS_675  ( usrclk2 )
PROCESS_676  ( usrclk2 )
PROCESS_677  ( usrclk2 )
PROCESS_678  ( usrclk )
PROCESS_679  ( usrclk )
PROCESS_680  ( usrclk2 )
PROCESS_681  ( usrclk2 )
PROCESS_682  ( usrclk2 )
PROCESS_683  ( usrclk2 )
PROCESS_684  ( usrclk2 )
PROCESS_685  ( usrclk2 )
PROCESS_686  ( usrclk2 )
PROCESS_687  ( usrclk )
PROCESS_688  ( usrclk )
PROCESS_689  ( usrclk2 )
PROCESS_690  ( usrclk2 )
PROCESS_691  ( usrclk2 )
PROCESS_692  ( usrclk2 )
PROCESS_693  ( usrclk2 )
PROCESS_694  ( usrclk2 )
PROCESS_695  ( usrclk2 )
PROCESS_696  ( usrclk )
PROCESS_697  ( usrclk )
PROCESS_698  ( usrclk2 )
PROCESS_699  ( usrclk2 )
PROCESS_700  ( usrclk2 )
PROCESS_701  ( usrclk2 )

Components

gig_eth_pcs_pma_v11_5_sync_block  <Entity gig_eth_pcs_pma_v11_5_sync_block>
gig_eth_pcs_pma_v11_5_GTWIZARD_init  <Entity gig_eth_pcs_pma_v11_5_GTWIZARD_init>
gig_eth_pcs_pma_v11_5_reset_sync  <Entity gig_eth_pcs_pma_v11_5_reset_sync>
gtwizard_v2_5_gbe_gth_init  <Entity gtwizard_v2_5_gbe_gth_init>
gtwizard_v2_5_gbe_gtx_init 

Signals

data_valid_reg  std_logic
data_valid_reg2  std_logic
cplllock  std_logic
gt_reset_rx  std_logic
gt_reset_tx  std_logic
resetdone_tx  std_logic
resetdone_rx  std_logic
pcsreset  std_logic
rxbufstatus  std_logic_vector ( 2 downto 0 )
txbufstatus  std_logic_vector ( 1 downto 0 )
rxbufstatus_reg  std_logic_vector ( 2 downto 0 )
txbufstatus_reg  std_logic_vector ( 1 downto 0 )
rxclkcorcnt_int  std_logic_vector ( 1 downto 0 )
toggle  std_logic
encommaalign_int  std_logic
txreset_int  std_logic
rxreset_int  std_logic
txdata_reg  std_logic_vector ( 7 downto 0 )
txchardispmode_reg  std_logic
txchardispval_reg  std_logic
txcharisk_reg  std_logic
txdata_double  std_logic_vector ( 15 downto 0 )
txchardispmode_double  std_logic_vector ( 1 downto 0 )
txchardispval_double  std_logic_vector ( 1 downto 0 )
txcharisk_double  std_logic_vector ( 1 downto 0 )
txdata_int  std_logic_vector ( 15 downto 0 )
txchardispmode_int  std_logic_vector ( 1 downto 0 )
txchardispval_int  std_logic_vector ( 1 downto 0 )
txcharisk_int  std_logic_vector ( 1 downto 0 )
rxchariscomma_int  std_logic_vector ( 1 downto 0 )
rxcharisk_int  std_logic_vector ( 1 downto 0 )
rxdata_int  std_logic_vector ( 15 downto 0 )
rxdisperr_int  std_logic_vector ( 1 downto 0 )
rxnotintable_int  std_logic_vector ( 1 downto 0 )
rxrundisp_int  std_logic_vector ( 1 downto 0 )
rxchariscomma_reg  std_logic_vector ( 1 downto 0 )
rxcharisk_reg  std_logic_vector ( 1 downto 0 )
rxdata_reg  std_logic_vector ( 15 downto 0 )
rxdisperr_reg  std_logic_vector ( 1 downto 0 )
rxnotintable_reg  std_logic_vector ( 1 downto 0 )
rxrundisp_reg  std_logic_vector ( 1 downto 0 )
rxchariscomma_double  std_logic_vector ( 1 downto 0 )
rxcharisk_double  std_logic_vector ( 1 downto 0 )
rxdata_double  std_logic_vector ( 15 downto 0 )
rxdisperr_double  std_logic_vector ( 1 downto 0 )
rxnotintable_double  std_logic_vector ( 1 downto 0 )
rxrundisp_double  std_logic_vector ( 1 downto 0 )
txpowerdown_int  std_logic_vector ( 1 downto 0 )
rxpowerdown_int  std_logic_vector ( 1 downto 0 )
txpowerdown_reg  std_logic := ' 0 '
txpowerdown_double  std_logic := ' 0 '
txpowerdown  std_logic := ' 0 '
rxpowerdown_reg  std_logic := ' 0 '
rxpowerdown_double  std_logic := ' 0 '
rxpowerdown  std_logic := ' 0 '

Instantiations

reclock_encommaalign  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
reclock_txreset  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
reclock_rxreset  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
gtwizard_inst  gig_eth_pcs_pma_v11_5_GTWIZARD_init <Entity gig_eth_pcs_pma_v11_5_GTWIZARD_init>
sync_block_data_valid  gig_eth_pcs_pma_v11_5_sync_block <Entity gig_eth_pcs_pma_v11_5_sync_block>
reclock_encommaalign  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
reclock_txreset  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
reclock_rxreset  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
gtwizard_inst  gtwizard_v2_5_gbe_gth_init <Entity gtwizard_v2_5_gbe_gth_init>
sync_block_data_valid  gig_eth_pcs_pma_v11_5_sync_block <Entity gig_eth_pcs_pma_v11_5_sync_block>
reclock_encommaalign  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
reclock_txreset  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
reclock_rxreset  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
gtwizard_inst  gtwizard_v2_5_gbe_gtx_init
sync_block_data_valid  gig_eth_pcs_pma_v11_5_sync_block <Entity gig_eth_pcs_pma_v11_5_sync_block>
reclock_encommaalign  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
reclock_txreset  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
reclock_rxreset  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
gtwizard_inst  gtwizard_v2_5_gbe_gtx_init
sync_block_data_valid  gig_eth_pcs_pma_v11_5_sync_block <Entity gig_eth_pcs_pma_v11_5_sync_block>
reclock_encommaalign  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
reclock_txreset  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
reclock_rxreset  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
gtwizard_inst  gig_eth_pcs_pma_v11_5_GTWIZARD_init <Entity gig_eth_pcs_pma_v11_5_GTWIZARD_init>
sync_block_data_valid  gig_eth_pcs_pma_v11_5_sync_block <Entity gig_eth_pcs_pma_v11_5_sync_block>
reclock_encommaalign  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
reclock_txreset  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
reclock_rxreset  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
gtwizard_inst  gtwizard_v2_5_gbe_gth_init <Entity gtwizard_v2_5_gbe_gth_init>
sync_block_data_valid  gig_eth_pcs_pma_v11_5_sync_block <Entity gig_eth_pcs_pma_v11_5_sync_block>
reclock_encommaalign  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
reclock_txreset  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
reclock_rxreset  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
gtwizard_inst  gtwizard_v2_5_gbe_gtx_init
sync_block_data_valid  gig_eth_pcs_pma_v11_5_sync_block <Entity gig_eth_pcs_pma_v11_5_sync_block>
reclock_encommaalign  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
reclock_txreset  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
reclock_rxreset  gig_eth_pcs_pma_v11_5_reset_sync <Entity gig_eth_pcs_pma_v11_5_reset_sync>
gtwizard_inst  gtwizard_v2_5_gbe_gtx_init
sync_block_data_valid  gig_eth_pcs_pma_v11_5_sync_block <Entity gig_eth_pcs_pma_v11_5_sync_block>

Member Function Documentation

◆ PROCESS_100()

PROCESS_100 (   usrclk2)

◆ PROCESS_101()

PROCESS_101 (   usrclk2  
)
Process

◆ PROCESS_102()

PROCESS_102 (   usrclk2  
)
Process

◆ PROCESS_103()

PROCESS_103 (   usrclk  
)
Process

◆ PROCESS_104()

PROCESS_104 (   usrclk  
)
Process

◆ PROCESS_105()

PROCESS_105 (   usrclk2  
)
Process

◆ PROCESS_106()

PROCESS_106 (   usrclk2  
)
Process

◆ PROCESS_107()

PROCESS_107 (   usrclk2)

◆ PROCESS_108()

PROCESS_108 (   usrclk2  
)
Process

◆ PROCESS_114()

PROCESS_114 (   usrclk2)

◆ PROCESS_115()

PROCESS_115 (   usrclk2  
)
Process

◆ PROCESS_116()

PROCESS_116 (   usrclk2  
)
Process

◆ PROCESS_117()

PROCESS_117 (   usrclk  
)
Process

◆ PROCESS_118()

PROCESS_118 (   usrclk  
)
Process

◆ PROCESS_119()

PROCESS_119 (   usrclk2  
)
Process

◆ PROCESS_120()

PROCESS_120 (   usrclk2  
)
Process

◆ PROCESS_121()

PROCESS_121 (   usrclk2)

◆ PROCESS_122()

PROCESS_122 (   usrclk2  
)
Process

◆ PROCESS_123()

PROCESS_123 (   usrclk2)

◆ PROCESS_124()

PROCESS_124 (   usrclk2  
)
Process

◆ PROCESS_125()

PROCESS_125 (   usrclk2  
)
Process

◆ PROCESS_126()

PROCESS_126 (   usrclk  
)
Process

◆ PROCESS_127()

PROCESS_127 (   usrclk  
)
Process

◆ PROCESS_128()

PROCESS_128 (   usrclk2  
)
Process

◆ PROCESS_129()

PROCESS_129 (   usrclk2  
)
Process

◆ PROCESS_130()

PROCESS_130 (   usrclk2)

◆ PROCESS_131()

PROCESS_131 (   usrclk2  
)
Process

◆ PROCESS_132()

PROCESS_132 (   usrclk2)

◆ PROCESS_133()

PROCESS_133 (   usrclk2  
)
Process

◆ PROCESS_134()

PROCESS_134 (   usrclk2  
)
Process

◆ PROCESS_135()

PROCESS_135 (   usrclk  
)
Process

◆ PROCESS_136()

PROCESS_136 (   usrclk  
)
Process

◆ PROCESS_137()

PROCESS_137 (   usrclk2  
)
Process

◆ PROCESS_138()

PROCESS_138 (   usrclk2  
)
Process

◆ PROCESS_139()

PROCESS_139 (   usrclk2)

◆ PROCESS_140()

PROCESS_140 (   usrclk2  
)
Process

◆ PROCESS_661()

PROCESS_661 (   usrclk2)

◆ PROCESS_662()

PROCESS_662 (   usrclk2  
)
Process

◆ PROCESS_663()

PROCESS_663 (   usrclk2  
)
Process

◆ PROCESS_664()

PROCESS_664 (   usrclk  
)
Process

◆ PROCESS_665()

PROCESS_665 (   usrclk  
)
Process

◆ PROCESS_666()

PROCESS_666 (   usrclk2  
)
Process

◆ PROCESS_667()

PROCESS_667 (   usrclk2  
)
Process

◆ PROCESS_668()

PROCESS_668 (   usrclk2)

◆ PROCESS_669()

PROCESS_669 (   usrclk2  
)
Process

◆ PROCESS_675()

PROCESS_675 (   usrclk2)

◆ PROCESS_676()

PROCESS_676 (   usrclk2  
)
Process

◆ PROCESS_677()

PROCESS_677 (   usrclk2  
)
Process

◆ PROCESS_678()

PROCESS_678 (   usrclk  
)
Process

◆ PROCESS_679()

PROCESS_679 (   usrclk  
)
Process

◆ PROCESS_680()

PROCESS_680 (   usrclk2  
)
Process

◆ PROCESS_681()

PROCESS_681 (   usrclk2  
)
Process

◆ PROCESS_682()

PROCESS_682 (   usrclk2)

◆ PROCESS_683()

PROCESS_683 (   usrclk2  
)
Process

◆ PROCESS_684()

PROCESS_684 (   usrclk2)

◆ PROCESS_685()

PROCESS_685 (   usrclk2  
)
Process

◆ PROCESS_686()

PROCESS_686 (   usrclk2  
)
Process

◆ PROCESS_687()

PROCESS_687 (   usrclk  
)
Process

◆ PROCESS_688()

PROCESS_688 (   usrclk  
)
Process

◆ PROCESS_689()

PROCESS_689 (   usrclk2  
)
Process

◆ PROCESS_690()

PROCESS_690 (   usrclk2  
)
Process

◆ PROCESS_691()

PROCESS_691 (   usrclk2)

◆ PROCESS_692()

PROCESS_692 (   usrclk2  
)
Process

◆ PROCESS_693()

PROCESS_693 (   usrclk2)

◆ PROCESS_694()

PROCESS_694 (   usrclk2  
)
Process

◆ PROCESS_695()

PROCESS_695 (   usrclk2  
)
Process

◆ PROCESS_696()

PROCESS_696 (   usrclk  
)
Process

◆ PROCESS_697()

PROCESS_697 (   usrclk  
)
Process

◆ PROCESS_698()

PROCESS_698 (   usrclk2  
)
Process

◆ PROCESS_699()

PROCESS_699 (   usrclk2  
)
Process

◆ PROCESS_700()

PROCESS_700 (   usrclk2)

◆ PROCESS_701()

PROCESS_701 (   usrclk2  
)
Process

Member Data Documentation

◆ cplllock

cplllock std_logic
Signal

◆ data_valid_reg

data_valid_reg std_logic
Signal

◆ data_valid_reg2

data_valid_reg2 std_logic
Signal

◆ encommaalign_int

encommaalign_int std_logic
Signal

◆ gig_eth_pcs_pma_v11_5_GTWIZARD_init

gig_eth_pcs_pma_v11_5_GTWIZARD_init
Component

◆ gig_eth_pcs_pma_v11_5_reset_sync

gig_eth_pcs_pma_v11_5_reset_sync
Component

◆ gig_eth_pcs_pma_v11_5_sync_block

gig_eth_pcs_pma_v11_5_sync_block
Component

◆ gt_reset_rx

gt_reset_rx std_logic
Signal

◆ gt_reset_tx

gt_reset_tx std_logic
Signal

◆ gtwizard_inst [1/8]

gtwizard_inst gig_eth_pcs_pma_v11_5_GTWIZARD_init
Instantiation

◆ gtwizard_inst [2/8]

gtwizard_inst gig_eth_pcs_pma_v11_5_GTWIZARD_init
Instantiation

◆ gtwizard_inst [3/8]

gtwizard_inst gtwizard_v2_5_gbe_gth_init
Instantiation

◆ gtwizard_inst [4/8]

gtwizard_inst gtwizard_v2_5_gbe_gth_init
Instantiation

◆ gtwizard_inst [5/8]

gtwizard_inst gtwizard_v2_5_gbe_gtx_init
Instantiation

◆ gtwizard_inst [6/8]

gtwizard_inst gtwizard_v2_5_gbe_gtx_init
Instantiation

◆ gtwizard_inst [7/8]

gtwizard_inst gtwizard_v2_5_gbe_gtx_init
Instantiation

◆ gtwizard_inst [8/8]

gtwizard_inst gtwizard_v2_5_gbe_gtx_init
Instantiation

◆ gtwizard_v2_5_gbe_gth_init

gtwizard_v2_5_gbe_gth_init
Component

◆ gtwizard_v2_5_gbe_gtx_init

gtwizard_v2_5_gbe_gtx_init
Component

◆ pcsreset

pcsreset std_logic
Signal

◆ reclock_encommaalign [1/8]

reclock_encommaalign gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_encommaalign [2/8]

reclock_encommaalign gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_encommaalign [3/8]

reclock_encommaalign gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_encommaalign [4/8]

reclock_encommaalign gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_encommaalign [5/8]

reclock_encommaalign gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_encommaalign [6/8]

reclock_encommaalign gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_encommaalign [7/8]

reclock_encommaalign gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_encommaalign [8/8]

reclock_encommaalign gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_rxreset [1/8]

reclock_rxreset gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_rxreset [2/8]

reclock_rxreset gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_rxreset [3/8]

reclock_rxreset gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_rxreset [4/8]

reclock_rxreset gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_rxreset [5/8]

reclock_rxreset gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_rxreset [6/8]

reclock_rxreset gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_rxreset [7/8]

reclock_rxreset gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_rxreset [8/8]

reclock_rxreset gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_txreset [1/8]

reclock_txreset gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_txreset [2/8]

reclock_txreset gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_txreset [3/8]

reclock_txreset gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_txreset [4/8]

reclock_txreset gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_txreset [5/8]

reclock_txreset gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_txreset [6/8]

reclock_txreset gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_txreset [7/8]

reclock_txreset gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ reclock_txreset [8/8]

reclock_txreset gig_eth_pcs_pma_v11_5_reset_sync
Instantiation

◆ resetdone_rx

resetdone_rx std_logic
Signal

◆ resetdone_tx

resetdone_tx std_logic
Signal

◆ rxbufstatus

rxbufstatus std_logic_vector ( 2 downto 0 )
Signal

◆ rxbufstatus_reg

rxbufstatus_reg std_logic_vector ( 2 downto 0 )
Signal

◆ rxchariscomma_double

rxchariscomma_double std_logic_vector ( 1 downto 0 )
Signal

◆ rxchariscomma_int

rxchariscomma_int std_logic_vector ( 1 downto 0 )
Signal

◆ rxchariscomma_reg

rxchariscomma_reg std_logic_vector ( 1 downto 0 )
Signal

◆ rxcharisk_double

rxcharisk_double std_logic_vector ( 1 downto 0 )
Signal

◆ rxcharisk_int

rxcharisk_int std_logic_vector ( 1 downto 0 )
Signal

◆ rxcharisk_reg

rxcharisk_reg std_logic_vector ( 1 downto 0 )
Signal

◆ rxclkcorcnt_int

rxclkcorcnt_int std_logic_vector ( 1 downto 0 )
Signal

◆ rxdata_double

rxdata_double std_logic_vector ( 15 downto 0 )
Signal

◆ rxdata_int

rxdata_int std_logic_vector ( 15 downto 0 )
Signal

◆ rxdata_reg

rxdata_reg std_logic_vector ( 15 downto 0 )
Signal

◆ rxdisperr_double

rxdisperr_double std_logic_vector ( 1 downto 0 )
Signal

◆ rxdisperr_int

rxdisperr_int std_logic_vector ( 1 downto 0 )
Signal

◆ rxdisperr_reg

rxdisperr_reg std_logic_vector ( 1 downto 0 )
Signal

◆ rxnotintable_double

rxnotintable_double std_logic_vector ( 1 downto 0 )
Signal

◆ rxnotintable_int

rxnotintable_int std_logic_vector ( 1 downto 0 )
Signal

◆ rxnotintable_reg

rxnotintable_reg std_logic_vector ( 1 downto 0 )
Signal

◆ rxpowerdown

rxpowerdown std_logic := ' 0 '
Signal

◆ rxpowerdown_double

rxpowerdown_double std_logic := ' 0 '
Signal

◆ rxpowerdown_int

rxpowerdown_int std_logic_vector ( 1 downto 0 )
Signal

◆ rxpowerdown_reg

rxpowerdown_reg std_logic := ' 0 '
Signal

◆ rxreset_int

rxreset_int std_logic
Signal

◆ rxrundisp_double

rxrundisp_double std_logic_vector ( 1 downto 0 )
Signal

◆ rxrundisp_int

rxrundisp_int std_logic_vector ( 1 downto 0 )
Signal

◆ rxrundisp_reg

rxrundisp_reg std_logic_vector ( 1 downto 0 )
Signal

◆ sync_block_data_valid [1/8]

sync_block_data_valid gig_eth_pcs_pma_v11_5_sync_block
Instantiation

◆ sync_block_data_valid [2/8]

sync_block_data_valid gig_eth_pcs_pma_v11_5_sync_block
Instantiation

◆ sync_block_data_valid [3/8]

sync_block_data_valid gig_eth_pcs_pma_v11_5_sync_block
Instantiation

◆ sync_block_data_valid [4/8]

sync_block_data_valid gig_eth_pcs_pma_v11_5_sync_block
Instantiation

◆ sync_block_data_valid [5/8]

sync_block_data_valid gig_eth_pcs_pma_v11_5_sync_block
Instantiation

◆ sync_block_data_valid [6/8]

sync_block_data_valid gig_eth_pcs_pma_v11_5_sync_block
Instantiation

◆ sync_block_data_valid [7/8]

sync_block_data_valid gig_eth_pcs_pma_v11_5_sync_block
Instantiation

◆ sync_block_data_valid [8/8]

sync_block_data_valid gig_eth_pcs_pma_v11_5_sync_block
Instantiation

◆ toggle

toggle std_logic
Signal

◆ txbufstatus

txbufstatus std_logic_vector ( 1 downto 0 )
Signal

◆ txbufstatus_reg

txbufstatus_reg std_logic_vector ( 1 downto 0 )
Signal

◆ txchardispmode_double

txchardispmode_double std_logic_vector ( 1 downto 0 )
Signal

◆ txchardispmode_int

txchardispmode_int std_logic_vector ( 1 downto 0 )
Signal

◆ txchardispmode_reg

txchardispmode_reg std_logic
Signal

◆ txchardispval_double

txchardispval_double std_logic_vector ( 1 downto 0 )
Signal

◆ txchardispval_int

txchardispval_int std_logic_vector ( 1 downto 0 )
Signal

◆ txchardispval_reg

txchardispval_reg std_logic
Signal

◆ txcharisk_double

txcharisk_double std_logic_vector ( 1 downto 0 )
Signal

◆ txcharisk_int

txcharisk_int std_logic_vector ( 1 downto 0 )
Signal

◆ txcharisk_reg

txcharisk_reg std_logic
Signal

◆ txdata_double

txdata_double std_logic_vector ( 15 downto 0 )
Signal

◆ txdata_int

txdata_int std_logic_vector ( 15 downto 0 )
Signal

◆ txdata_reg

txdata_reg std_logic_vector ( 7 downto 0 )
Signal

◆ txpowerdown

txpowerdown std_logic := ' 0 '
Signal

◆ txpowerdown_double

txpowerdown_double std_logic := ' 0 '
Signal

◆ txpowerdown_int

txpowerdown_int std_logic_vector ( 1 downto 0 )
Signal

◆ txpowerdown_reg

txpowerdown_reg std_logic := ' 0 '
Signal

◆ txreset_int

txreset_int std_logic
Signal
The documentation for this class was generated from the following files:
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