gtwizard_v2_3_gbe Entity Reference

Inheritance diagram for gtwizard_v2_3_gbe:

Collaboration diagram for gtwizard_v2_3_gbe:

Entities
RTL	architecture

Libraries
ieee
UNISIM

Use Clauses
std_logic_1164
numeric_std
VCOMPONENTS

Generics
QPLL_FBDIV_TOP	integer := 16
WRAPPER_SIM_GTRESET_SPEEDUP	string := " false "
RX_DFE_KL_CFG2_IN	bit_vector := X " 3010D90C "
PMA_RSV_IN	bit_vector := x " 00018480 "
SIM_VERSION	string := " 4.0 "

Ports
GT0_DRPADDR_IN	in std_logic_vector ( 8 downto 0 )
GT0_DRPCLK_IN	in std_logic
GT0_DRPDI_IN	in std_logic_vector ( 15 downto 0 )
GT0_DRPDO_OUT	out std_logic_vector ( 15 downto 0 )
GT0_DRPEN_IN	in std_logic
GT0_DRPRDY_OUT	out std_logic
GT0_DRPWE_IN	in std_logic
GT0_GTREFCLK0_IN	in std_logic
GT0_CPLLFBCLKLOST_OUT	out std_logic
GT0_CPLLLOCK_OUT	out std_logic
GT0_CPLLLOCKDETCLK_IN	in std_logic
GT0_CPLLREFCLKLOST_OUT	out std_logic
GT0_CPLLRESET_IN	in std_logic
GT0_EYESCANDATAERROR_OUT	out std_logic
GT0_LOOPBACK_IN	in std_logic_vector ( 2 downto 0 )
GT0_RXPD_IN	in std_logic_vector ( 1 downto 0 )
GT0_TXPD_IN	in std_logic_vector ( 1 downto 0 )
GT0_RXUSERRDY_IN	in std_logic
GT0_RXCHARISCOMMA_OUT	out std_logic_vector ( 1 downto 0 )
GT0_RXCHARISK_OUT	out std_logic_vector ( 1 downto 0 )
GT0_RXDISPERR_OUT	out std_logic_vector ( 1 downto 0 )
GT0_RXNOTINTABLE_OUT	out std_logic_vector ( 1 downto 0 )
GT0_RXCLKCORCNT_OUT	out std_logic_vector ( 1 downto 0 )
GT0_RXMCOMMAALIGNEN_IN	in std_logic
GT0_RXPCOMMAALIGNEN_IN	in std_logic
GT0_GTRXRESET_IN	in std_logic
GT0_RXDATA_OUT	out std_logic_vector ( 15 downto 0 )
GT0_RXOUTCLK_OUT	out std_logic
GT0_RXPCSRESET_IN	in std_logic
GT0_RXPMARESET_IN	in std_logic
GT0_RXUSRCLK_IN	in std_logic
GT0_RXUSRCLK2_IN	in std_logic
GT0_RXDFEAGCHOLD_IN	in std_logic
GT0_RXDFELPMRESET_IN	in std_logic
GT0_RXMONITOROUT_OUT	out std_logic_vector ( 6 downto 0 )
GT0_RXMONITORSEL_IN	in std_logic_vector ( 1 downto 0 )
GT0_GTXRXN_IN	in std_logic
GT0_GTXRXP_IN	in std_logic
GT0_RXCDRLOCK_OUT	out std_logic
GT0_RXELECIDLE_OUT	out std_logic
GT0_RXBUFRESET_IN	in std_logic
GT0_RXBUFSTATUS_OUT	out std_logic_vector ( 2 downto 0 )
GT0_RXRESETDONE_OUT	out std_logic
GT0_TXUSERRDY_IN	in std_logic
GT0_TXCHARDISPMODE_IN	in std_logic_vector ( 1 downto 0 )
GT0_TXCHARDISPVAL_IN	in std_logic_vector ( 1 downto 0 )
GT0_TXCHARISK_IN	in std_logic_vector ( 1 downto 0 )
GT0_TXBUFSTATUS_OUT	out std_logic_vector ( 1 downto 0 )
GT0_GTTXRESET_IN	in std_logic
GT0_TXDATA_IN	in std_logic_vector ( 15 downto 0 )
GT0_TXOUTCLK_OUT	out std_logic
GT0_TXOUTCLKFABRIC_OUT	out std_logic
GT0_TXOUTCLKPCS_OUT	out std_logic
GT0_TXPCSRESET_IN	in std_logic
GT0_TXUSRCLK_IN	in std_logic
GT0_TXUSRCLK2_IN	in std_logic
GT0_GTXTXN_OUT	out std_logic
GT0_GTXTXP_OUT	out std_logic
GT0_TXRESETDONE_OUT	out std_logic
GT0_GTREFCLK0_COMMON_IN	in std_logic
GT0_QPLLLOCK_OUT	out std_logic
GT0_QPLLLOCKDETCLK_IN	in std_logic
GT0_QPLLREFCLKLOST_OUT	out std_logic
GT0_QPLLRESET_IN	in std_logic

Member Data Documentation

GT0_CPLLFBCLKLOST_OUT

GT0_CPLLFBCLKLOST_OUT out std_logic

Port

GT0_CPLLLOCK_OUT

GT0_CPLLLOCK_OUT out std_logic

Port

GT0_CPLLLOCKDETCLK_IN

GT0_CPLLLOCKDETCLK_IN in std_logic

Port

GT0_CPLLREFCLKLOST_OUT

GT0_CPLLREFCLKLOST_OUT out std_logic

Port

GT0_CPLLRESET_IN

GT0_CPLLRESET_IN in std_logic

Port

GT0_DRPADDR_IN

GT0_DRPADDR_IN in std_logic_vector ( 8 downto 0 )

Port

GT0_DRPCLK_IN

GT0_DRPCLK_IN in std_logic

Port

GT0_DRPDI_IN

GT0_DRPDI_IN in std_logic_vector ( 15 downto 0 )

Port

GT0_DRPDO_OUT

GT0_DRPDO_OUT out std_logic_vector ( 15 downto 0 )

Port

GT0_DRPEN_IN

GT0_DRPEN_IN in std_logic

Port

GT0_DRPRDY_OUT

GT0_DRPRDY_OUT out std_logic

Port

GT0_DRPWE_IN

GT0_DRPWE_IN in std_logic

Port

GT0_EYESCANDATAERROR_OUT

GT0_EYESCANDATAERROR_OUT out std_logic

Port

GT0_GTREFCLK0_COMMON_IN

GT0_GTREFCLK0_COMMON_IN in std_logic

Port

GT0_GTREFCLK0_IN

GT0_GTREFCLK0_IN in std_logic

Port

GT0_GTRXRESET_IN

GT0_GTRXRESET_IN in std_logic

Port

GT0_GTTXRESET_IN

GT0_GTTXRESET_IN in std_logic

Port

GT0_GTXRXN_IN

GT0_GTXRXN_IN in std_logic

Port

GT0_GTXRXP_IN

GT0_GTXRXP_IN in std_logic

Port

GT0_GTXTXN_OUT

GT0_GTXTXN_OUT out std_logic

Port

GT0_GTXTXP_OUT

GT0_GTXTXP_OUT out std_logic

Port

GT0_LOOPBACK_IN

GT0_LOOPBACK_IN in std_logic_vector ( 2 downto 0 )

Port

GT0_QPLLLOCK_OUT

GT0_QPLLLOCK_OUT out std_logic

Port

GT0_QPLLLOCKDETCLK_IN

GT0_QPLLLOCKDETCLK_IN in std_logic

Port

GT0_QPLLREFCLKLOST_OUT

GT0_QPLLREFCLKLOST_OUT out std_logic

Port

GT0_QPLLRESET_IN

GT0_QPLLRESET_IN in std_logic

Port

GT0_RXBUFRESET_IN

GT0_RXBUFRESET_IN in std_logic

Port

GT0_RXBUFSTATUS_OUT

GT0_RXBUFSTATUS_OUT out std_logic_vector ( 2 downto 0 )

Port

GT0_RXCDRLOCK_OUT

GT0_RXCDRLOCK_OUT out std_logic

Port

GT0_RXCHARISCOMMA_OUT

GT0_RXCHARISCOMMA_OUT out std_logic_vector ( 1 downto 0 )

Port

GT0_RXCHARISK_OUT

GT0_RXCHARISK_OUT out std_logic_vector ( 1 downto 0 )

Port

GT0_RXCLKCORCNT_OUT

GT0_RXCLKCORCNT_OUT out std_logic_vector ( 1 downto 0 )

Port

GT0_RXDATA_OUT

GT0_RXDATA_OUT out std_logic_vector ( 15 downto 0 )

Port

GT0_RXDFEAGCHOLD_IN

GT0_RXDFEAGCHOLD_IN in std_logic

Port

GT0_RXDFELPMRESET_IN

GT0_RXDFELPMRESET_IN in std_logic

Port

GT0_RXDISPERR_OUT

GT0_RXDISPERR_OUT out std_logic_vector ( 1 downto 0 )

Port

GT0_RXELECIDLE_OUT

GT0_RXELECIDLE_OUT out std_logic

Port

GT0_RXMCOMMAALIGNEN_IN

GT0_RXMCOMMAALIGNEN_IN in std_logic

Port

GT0_RXMONITOROUT_OUT

GT0_RXMONITOROUT_OUT out std_logic_vector ( 6 downto 0 )

Port

GT0_RXMONITORSEL_IN

GT0_RXMONITORSEL_IN in std_logic_vector ( 1 downto 0 )

Port

GT0_RXNOTINTABLE_OUT

GT0_RXNOTINTABLE_OUT out std_logic_vector ( 1 downto 0 )

Port

GT0_RXOUTCLK_OUT

GT0_RXOUTCLK_OUT out std_logic

Port

GT0_RXPCOMMAALIGNEN_IN

GT0_RXPCOMMAALIGNEN_IN in std_logic

Port

GT0_RXPCSRESET_IN

GT0_RXPCSRESET_IN in std_logic

Port

GT0_RXPD_IN

GT0_RXPD_IN in std_logic_vector ( 1 downto 0 )

Port

GT0_RXPMARESET_IN

GT0_RXPMARESET_IN in std_logic

Port

GT0_RXRESETDONE_OUT

GT0_RXRESETDONE_OUT out std_logic

Port

GT0_RXUSERRDY_IN

GT0_RXUSERRDY_IN in std_logic

Port

GT0_RXUSRCLK2_IN

GT0_RXUSRCLK2_IN in std_logic

Port

GT0_RXUSRCLK_IN

GT0_RXUSRCLK_IN in std_logic

Port

GT0_TXBUFSTATUS_OUT

GT0_TXBUFSTATUS_OUT out std_logic_vector ( 1 downto 0 )

Port

GT0_TXCHARDISPMODE_IN

GT0_TXCHARDISPMODE_IN in std_logic_vector ( 1 downto 0 )

Port

GT0_TXCHARDISPVAL_IN

GT0_TXCHARDISPVAL_IN in std_logic_vector ( 1 downto 0 )

Port

GT0_TXCHARISK_IN

GT0_TXCHARISK_IN in std_logic_vector ( 1 downto 0 )

Port

GT0_TXDATA_IN

GT0_TXDATA_IN in std_logic_vector ( 15 downto 0 )

Port

GT0_TXOUTCLK_OUT

GT0_TXOUTCLK_OUT out std_logic

Port

GT0_TXOUTCLKFABRIC_OUT

GT0_TXOUTCLKFABRIC_OUT out std_logic

Port

GT0_TXOUTCLKPCS_OUT

GT0_TXOUTCLKPCS_OUT out std_logic

Port

GT0_TXPCSRESET_IN

GT0_TXPCSRESET_IN in std_logic

Port

GT0_TXPD_IN

GT0_TXPD_IN in std_logic_vector ( 1 downto 0 )

Port

GT0_TXRESETDONE_OUT

GT0_TXRESETDONE_OUT out std_logic

Port

GT0_TXUSERRDY_IN

GT0_TXUSERRDY_IN in std_logic

Port

GT0_TXUSRCLK2_IN

GT0_TXUSRCLK2_IN in std_logic

Port

GT0_TXUSRCLK_IN

GT0_TXUSRCLK_IN in std_logic

Port

ieee

ieee

Library

numeric_std

numeric_std

Package

PMA_RSV_IN

PMA_RSV_IN bit_vector := x " 00018480 "

Generic

QPLL_FBDIV_TOP

QPLL_FBDIV_TOP integer := 16

Generic

RX_DFE_KL_CFG2_IN

RX_DFE_KL_CFG2_IN bit_vector := X " 3010D90C "

Generic

SIM_VERSION

SIM_VERSION string := " 4.0 "

Generic

std_logic_1164

std_logic_1164

Package

UNISIM

UNISIM

Library

VCOMPONENTS

VCOMPONENTS

Package

WRAPPER_SIM_GTRESET_SPEEDUP

WRAPPER_SIM_GTRESET_SPEEDUP string := " false "

Generic

---

The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/gtwizard_v2_3_gbe/gtwizard_v2_3_gbe.vhd