RTL Architecture Reference

Collaboration diagram for RTL:

Functions
bit_vector	conv_qpll_fbdiv_top ( qpllfbdiv_top: in in integer )	[ impure ]
bit	conv_qpll_fbdiv_ratio ( qpllfbdiv_top: in in integer )	[ impure ]
bit_vector	conv_qpll_fbdiv_top ( qpllfbdiv_top: in in integer )	[ impure ]
bit	conv_qpll_fbdiv_ratio ( qpllfbdiv_top: in in integer )	[ impure ]

Components
gtwizard_v2_3_gbe_GT	<Entity gtwizard_v2_3_gbe_GT>

Constants
DLY	time := 1 ns
QPLL_FBDIV_IN	bit_vector ( 9 downto 0 ) := conv_qpll_fbdiv_top ( QPLL_FBDIV_TOP )
QPLL_FBDIV_RATIO	bit := conv_qpll_fbdiv_ratio ( QPLL_FBDIV_TOP )

Signals
tied_to_ground_i	std_logic
tied_to_ground_vec_i	std_logic_vector ( 63 downto 0 )
tied_to_vcc_i	std_logic
gt0_qplloutclk_i	std_logic
gt0_qplloutrefclk_i	std_logic
gt0_mgtrefclktx_i	std_logic_vector ( 1 downto 0 )
gt0_mgtrefclkrx_i	std_logic_vector ( 1 downto 0 )
gt0_qpllclk_i	std_logic
gt0_qpllrefclk_i	std_logic

Attributes
CORE_GENERATION_INFO	string
CORE_GENERATION_INFO	RTL : architecture is " gtwizard_v2_3_gbe , gtwizard_v2_3 , {protocol_file = gigabit_ethernet_CC} "

Instantiations
gt0_gtwizard_v2_3_gbe_i	gtwizard_v2_3_gbe_GT <Entity gtwizard_v2_3_gbe_GT>
gtxe2_common_0_i	gtxe2_common
gt0_gtwizard_v2_3_gbe_i	gtwizard_v2_3_gbe_GT <Entity gtwizard_v2_3_gbe_GT>
gtxe2_common_0_i	gtxe2_common

Member Function Documentation

conv_qpll_fbdiv_ratio() [1/2]

bit conv_qpll_fbdiv_ratio (   qpllfbdiv_top in in integer   ) impure

Function

conv_qpll_fbdiv_ratio() [2/2]

bit conv_qpll_fbdiv_ratio (   qpllfbdiv_top in in integer   ) impure

Function

conv_qpll_fbdiv_top() [1/2]

bit_vector conv_qpll_fbdiv_top (   qpllfbdiv_top in in integer   ) impure

Function

conv_qpll_fbdiv_top() [2/2]

bit_vector conv_qpll_fbdiv_top (   qpllfbdiv_top in in integer   ) impure

Function

Member Data Documentation

CORE_GENERATION_INFO [1/2]

CORE_GENERATION_INFO string

Attribute

CORE_GENERATION_INFO [2/2]

CORE_GENERATION_INFO RTL : architecture is " gtwizard_v2_3_gbe , gtwizard_v2_3 , {protocol_file = gigabit_ethernet_CC} "

Attribute

DLY

DLY time := 1 ns

Constant

gt0_gtwizard_v2_3_gbe_i [1/2]

gt0_gtwizard_v2_3_gbe_i gtwizard_v2_3_gbe_GT

Instantiation

gt0_gtwizard_v2_3_gbe_i [2/2]

gt0_gtwizard_v2_3_gbe_i gtwizard_v2_3_gbe_GT

Instantiation

gt0_mgtrefclkrx_i

gt0_mgtrefclkrx_i std_logic_vector ( 1 downto 0 )

Signal

gt0_mgtrefclktx_i

gt0_mgtrefclktx_i std_logic_vector ( 1 downto 0 )

Signal

gt0_qpllclk_i

gt0_qpllclk_i std_logic

Signal

gt0_qplloutclk_i

gt0_qplloutclk_i std_logic

Signal

gt0_qplloutrefclk_i

gt0_qplloutrefclk_i std_logic

Signal

gt0_qpllrefclk_i

gt0_qpllrefclk_i std_logic

Signal

gtwizard_v2_3_gbe_GT

gtwizard_v2_3_gbe_GT

Component

gtxe2_common_0_i [1/2]

gtxe2_common_0_i gtxe2_common

Instantiation

gtxe2_common_0_i [2/2]

gtxe2_common_0_i gtxe2_common

Instantiation

QPLL_FBDIV_IN

QPLL_FBDIV_IN bit_vector ( 9 downto 0 ) := conv_qpll_fbdiv_top ( QPLL_FBDIV_TOP )

Constant

QPLL_FBDIV_RATIO

QPLL_FBDIV_RATIO bit := conv_qpll_fbdiv_ratio ( QPLL_FBDIV_TOP )

Constant

tied_to_ground_i

tied_to_ground_i std_logic

Signal

tied_to_ground_vec_i

tied_to_ground_vec_i std_logic_vector ( 63 downto 0 )

Signal

tied_to_vcc_i

tied_to_vcc_i std_logic

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/gtwizard_v2_3_gbe/gtwizard_v2_3_gbe.vhd