gtwizard_v2_3_gbe_gth_RECCLK_MONITOR Entity Reference

Inheritance diagram for gtwizard_v2_3_gbe_gth_RECCLK_MONITOR:

Entities
RTL	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
STD_LOGIC_ARITH
STD_LOGIC_UNSIGNED

Generics
COUNTER_UPPER_VALUE	integer := 20
GCLK_COUNTER_UPPER_VALUE	integer := 20
CLOCK_PULSES	integer := 5000
EXAMPLE_SIMULATION	integer := 0

Ports
GT_RST	in std_logic
REF_CLK	in std_logic
RX_REC_CLK0	in std_logic
SYSTEM_CLK	in std_logic
PLL_LK_DET	in std_logic
RECCLK_STABLE	out std_logic
EXEC_RESTART	out std_logic

Member Data Documentation

CLOCK_PULSES

CLOCK_PULSES integer := 5000

Generic

COUNTER_UPPER_VALUE

COUNTER_UPPER_VALUE integer := 20

Generic

EXAMPLE_SIMULATION

EXAMPLE_SIMULATION integer := 0

Generic

EXEC_RESTART

EXEC_RESTART out std_logic

Port

GCLK_COUNTER_UPPER_VALUE

GCLK_COUNTER_UPPER_VALUE integer := 20

Generic

GT_RST

GT_RST in std_logic

Port

IEEE

IEEE

Library

PLL_LK_DET

PLL_LK_DET in std_logic

Port

RECCLK_STABLE

RECCLK_STABLE out std_logic

Port

REF_CLK

REF_CLK in std_logic

Port

RX_REC_CLK0

RX_REC_CLK0 in std_logic

Port

STD_LOGIC_1164

STD_LOGIC_1164

Package

STD_LOGIC_ARITH

STD_LOGIC_ARITH

Package

STD_LOGIC_UNSIGNED

STD_LOGIC_UNSIGNED

Package

SYSTEM_CLK

SYSTEM_CLK in std_logic

Port

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/gtwizard_v2_3_gbe_gth/gtwizard_v2_3_gbe_gth_recclk_monitor.vhd