My Project  v0.0.16
Types | Signals | Attributes | Constants | Functions | Processes
RTL Architecture Reference

Functions

boolean   simulation_func ( )
boolean   simulation_func ( )

Processes

PROCESS_159  ( RX_REC_CLK0 )
PROCESS_160  ( RX_REC_CLK0 )
PROCESS_161  ( REF_CLK )
PROCESS_162  ( REF_CLK )
PROCESS_163  ( SYSTEM_CLK )
PROCESS_164  ( SYSTEM_CLK )
PROCESS_165  ( SYSTEM_CLK )
PROCESS_166  ( SYSTEM_CLK )
PROCESS_167  ( SYSTEM_CLK )
PROCESS_168  ( SYSTEM_CLK )
PROCESS_169  ( SYSTEM_CLK )
PROCESS_720  ( RX_REC_CLK0 )
PROCESS_721  ( RX_REC_CLK0 )
PROCESS_722  ( REF_CLK )
PROCESS_723  ( REF_CLK )
PROCESS_724  ( SYSTEM_CLK )
PROCESS_725  ( SYSTEM_CLK )
PROCESS_726  ( SYSTEM_CLK )
PROCESS_727  ( SYSTEM_CLK )
PROCESS_728  ( SYSTEM_CLK )
PROCESS_729  ( SYSTEM_CLK )
PROCESS_730  ( SYSTEM_CLK )

Constants

simulation  boolean := simulation_func

Types

FSM ( WAIT_FOR_LOCK , REFCLK_EVENT , CALC_PPM_DIFF , CHECK_SIGN , COMP_CNTR , RESTART )

Signals

state  FSM
ref_clk_cnt  std_logic_vector ( COUNTER_UPPER_VALUE - 1 downto 0 )
rec_clk0_cnt  std_logic_vector ( COUNTER_UPPER_VALUE - 1 downto 0 ) := ( others = > ' 0 ' )
rec_clk0_msb  std_logic_vector ( 2 downto 1 )
ref_clk_msb  std_logic_vector ( 2 downto 1 )
rec_clk_0_msb_meta  std_logic
ref_clk_msb_meta  std_logic
sys_clk_counter  std_logic_vector ( GCLK_COUNTER_UPPER_VALUE - 1 downto 0 )
rec_clk0_compare_cnt_latch  std_logic_vector ( GCLK_COUNTER_UPPER_VALUE - 1 downto 0 )
ref_clk_compare_cnt_latch  std_logic_vector ( GCLK_COUNTER_UPPER_VALUE - 1 downto 0 )
g_clk_rst_meta  std_logic
g_clk_rst_sync  std_logic
gt_pll_locked_meta  std_logic
gt_pll_locked_sync  std_logic
reset_logic_rec0_meta  std_logic
reset_logic_rec0_sync  std_logic
reset_logic_ref_meta  std_logic
reset_logic_ref_sync  std_logic
rec_clk0_edge_event  std_logic
ref_clk_edge_event  std_logic_vector ( 1 downto 0 )
ppm0  std_logic_vector ( GCLK_COUNTER_UPPER_VALUE - 1 downto 0 )
recclk_stable0  std_logic
reset_logic  std_logic_vector ( 3 downto 0 )
ref_clk_edge_rt  std_logic_vector ( 1 downto 0 )
g_clk_rst  std_logic
gt_pll_locked  std_logic
rec_clk0_edge  std_logic
ref_clk_edge  std_logic
recclk_stable0_int  std_logic := ' 0 '

Attributes

syn_keep  boolean
syn_keep  rec_clk_0_msb_meta : signal is true
syn_keep  ref_clk_msb_meta : signal is true
syn_keep  g_clk_rst_meta : signal is true
syn_keep  gt_pll_locked_meta : signal is true
syn_keep  reset_logic_rec0_meta : signal is true
syn_keep  reset_logic_ref_meta : signal is true

Member Function Documentation

◆ PROCESS_159()

PROCESS_159 (   RX_REC_CLK0  
)
Process

◆ PROCESS_160()

PROCESS_160 (   RX_REC_CLK0  
)
Process

◆ PROCESS_161()

PROCESS_161 (   REF_CLK  
)
Process

◆ PROCESS_162()

PROCESS_162 (   REF_CLK  
)
Process

◆ PROCESS_163()

PROCESS_163 (   SYSTEM_CLK  
)
Process

◆ PROCESS_164()

PROCESS_164 (   SYSTEM_CLK  
)
Process

◆ PROCESS_165()

PROCESS_165 (   SYSTEM_CLK  
)
Process

◆ PROCESS_166()

PROCESS_166 (   SYSTEM_CLK  
)
Process

◆ PROCESS_167()

PROCESS_167 (   SYSTEM_CLK  
)
Process

◆ PROCESS_168()

PROCESS_168 (   SYSTEM_CLK  
)
Process

◆ PROCESS_169()

PROCESS_169 (   SYSTEM_CLK  
)
Process

◆ PROCESS_720()

PROCESS_720 (   RX_REC_CLK0  
)
Process

◆ PROCESS_721()

PROCESS_721 (   RX_REC_CLK0  
)
Process

◆ PROCESS_722()

PROCESS_722 (   REF_CLK  
)
Process

◆ PROCESS_723()

PROCESS_723 (   REF_CLK  
)
Process

◆ PROCESS_724()

PROCESS_724 (   SYSTEM_CLK  
)
Process

◆ PROCESS_725()

PROCESS_725 (   SYSTEM_CLK  
)
Process

◆ PROCESS_726()

PROCESS_726 (   SYSTEM_CLK  
)
Process

◆ PROCESS_727()

PROCESS_727 (   SYSTEM_CLK  
)
Process

◆ PROCESS_728()

PROCESS_728 (   SYSTEM_CLK  
)
Process

◆ PROCESS_729()

PROCESS_729 (   SYSTEM_CLK  
)
Process

◆ PROCESS_730()

PROCESS_730 (   SYSTEM_CLK  
)
Process

◆ simulation_func() [1/2]

boolean simulation_func ( )
Function

◆ simulation_func() [2/2]

boolean simulation_func ( )
Function

Member Data Documentation

◆ FSM

FSM ( WAIT_FOR_LOCK , REFCLK_EVENT , CALC_PPM_DIFF , CHECK_SIGN , COMP_CNTR , RESTART )
Type

◆ g_clk_rst

g_clk_rst std_logic
Signal

◆ g_clk_rst_meta

g_clk_rst_meta std_logic
Signal

◆ g_clk_rst_sync

g_clk_rst_sync std_logic
Signal

◆ gt_pll_locked

gt_pll_locked std_logic
Signal

◆ gt_pll_locked_meta

gt_pll_locked_meta std_logic
Signal

◆ gt_pll_locked_sync

gt_pll_locked_sync std_logic
Signal

◆ ppm0

ppm0 std_logic_vector ( GCLK_COUNTER_UPPER_VALUE - 1 downto 0 )
Signal

◆ rec_clk0_cnt

rec_clk0_cnt std_logic_vector ( COUNTER_UPPER_VALUE - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

◆ rec_clk0_compare_cnt_latch

rec_clk0_compare_cnt_latch std_logic_vector ( GCLK_COUNTER_UPPER_VALUE - 1 downto 0 )
Signal

◆ rec_clk0_edge

rec_clk0_edge std_logic
Signal

◆ rec_clk0_edge_event

rec_clk0_edge_event std_logic
Signal

◆ rec_clk0_msb

rec_clk0_msb std_logic_vector ( 2 downto 1 )
Signal

◆ rec_clk_0_msb_meta

rec_clk_0_msb_meta std_logic
Signal

◆ recclk_stable0

recclk_stable0 std_logic
Signal

◆ recclk_stable0_int

recclk_stable0_int std_logic := ' 0 '
Signal

◆ ref_clk_cnt

ref_clk_cnt std_logic_vector ( COUNTER_UPPER_VALUE - 1 downto 0 )
Signal

◆ ref_clk_compare_cnt_latch

ref_clk_compare_cnt_latch std_logic_vector ( GCLK_COUNTER_UPPER_VALUE - 1 downto 0 )
Signal

◆ ref_clk_edge

ref_clk_edge std_logic
Signal

◆ ref_clk_edge_event

ref_clk_edge_event std_logic_vector ( 1 downto 0 )
Signal

◆ ref_clk_edge_rt

ref_clk_edge_rt std_logic_vector ( 1 downto 0 )
Signal

◆ ref_clk_msb

ref_clk_msb std_logic_vector ( 2 downto 1 )
Signal

◆ ref_clk_msb_meta

ref_clk_msb_meta std_logic
Signal

◆ reset_logic

reset_logic std_logic_vector ( 3 downto 0 )
Signal

◆ reset_logic_rec0_meta

reset_logic_rec0_meta std_logic
Signal

◆ reset_logic_rec0_sync

reset_logic_rec0_sync std_logic
Signal

◆ reset_logic_ref_meta

reset_logic_ref_meta std_logic
Signal

◆ reset_logic_ref_sync

reset_logic_ref_sync std_logic
Signal

◆ simulation

simulation boolean := simulation_func
Constant

◆ state

state FSM
Signal

◆ syn_keep [1/7]

syn_keep boolean
Attribute

◆ syn_keep [2/7]

syn_keep rec_clk_0_msb_meta : signal is true
Attribute

◆ syn_keep [3/7]

syn_keep ref_clk_msb_meta : signal is true
Attribute

◆ syn_keep [4/7]

syn_keep g_clk_rst_meta : signal is true
Attribute

◆ syn_keep [5/7]

syn_keep gt_pll_locked_meta : signal is true
Attribute

◆ syn_keep [6/7]

syn_keep reset_logic_rec0_meta : signal is true
Attribute

◆ syn_keep [7/7]

syn_keep reset_logic_ref_meta : signal is true
Attribute

◆ sys_clk_counter

sys_clk_counter std_logic_vector ( GCLK_COUNTER_UPPER_VALUE - 1 downto 0 )
Signal
The documentation for this class was generated from the following file:
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