RTL Architecture Reference

Functions
integer	get_cdrlock_time ( is_sim: in in integer )
integer	get_lpm_adapt_lock_time ( is_sim: in in integer )
integer	get_cdrlock_time ( is_sim: in in integer )
integer	get_lpm_adapt_lock_time ( is_sim: in in integer )

Processes
cdrlock_timeout	( SYSCLK_IN )
cdrlock_timeout	( SYSCLK_IN )

Components
gtwizard_v2_3_gbe	<Entity gtwizard_v2_3_gbe>
gtwizard_v2_3_gbe_TX_STARTUP_FSM	<Entity gtwizard_v2_3_gbe_TX_STARTUP_FSM>
gtwizard_v2_3_gbe_RX_STARTUP_FSM	<Entity gtwizard_v2_3_gbe_RX_STARTUP_FSM>
gtwizard_v2_3_gbe_RECCLK_MONITOR	<Entity gtwizard_v2_3_gbe_RECCLK_MONITOR>

Constants
DLY	time := 1 ns
STABLE_CLOCK_PERIOD	integer := 8
RX_CDRLOCK_TIME	integer := get_cdrlock_time ( EXAMPLE_SIMULATION )
WAIT_TIME_CDRLOCK	integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD
LPM_ADAPT_LOCK_TIMER	integer := get_lpm_adapt_lock_time ( EXAMPLE_SIMULATION )
DFE_ADAPT_LOCK_TIMER	integer := integer ( ( 13 * 100 ) / integer ( 1 . 25 ) )

Signals
gt0_cpllreset_i	std_logic
gt0_cpllreset_t	std_logic
gt0_cpllrefclklost_i	std_logic
gt0_cplllock_i	std_logic
gt0_txresetdone_i	std_logic
gt0_rxresetdone_i	std_logic
gt0_gttxreset_i	std_logic
gt0_gttxreset_t	std_logic
gt0_gttxreset_gt	std_logic
gt0_gtrxreset_i	std_logic
gt0_gtrxreset_t	std_logic
gt0_gtrxreset_gt	std_logic
gt0_txpcsreset_i	std_logic
gt0_rxpcsreset_i	std_logic
gt0_rxpmareset_i	std_logic
gt0_rxdfelpmreset_i	std_logic
gt0_txuserrdy_i	std_logic
gt0_txuserrdy_t	std_logic
gt0_rxuserrdy_i	std_logic
gt0_rxuserrdy_t	std_logic
gt0_rxdfeagchold_i	std_logic
gt0_rxdfelfhold_i	std_logic
gt0_rxlpmlfhold_i	std_logic
gt0_rxlpmhfhold_i	std_logic
gt0_drpaddr_i	std_logic_vector ( 8 downto 0 )
gt0_drpdi_i	std_logic_vector ( 15 downto 0 )
gt0_drpdo_o	std_logic_vector ( 15 downto 0 )
gt0_drpen_i	std_logic
gt0_drpwe_i	std_logic
gt0_drprdy_o	std_logic
gt0_drpaddr_int	std_logic_vector ( 8 downto 0 )
gt0_drpdi_int	std_logic_vector ( 15 downto 0 )
gt0_drpdo_int	std_logic_vector ( 15 downto 0 )
gt0_drpen_int	std_logic
gt0_drpwe_int	std_logic
gt0_drprdy_int	std_logic
gt0_rxmonitorout_o	std_logic_vector ( 6 downto 0 )
gt0_rxmonitorsel_i	std_logic_vector ( 1 downto 0 )
gt0_adapt_done	std_logic
gt0_qpllreset_i	std_logic
gt0_qpllreset_t	std_logic
gt0_qpllrefclklost_i	std_logic
gt0_qplllock_i	std_logic
tied_to_ground_i	std_logic
tied_to_vcc_i	std_logic
gt0_rxoutclk_i	std_logic
gt0_rxoutclk_i_buf	std_logic
gt0_recclk_stable_i	std_logic
gt0_recclk_mon_i	std_logic
gt0_recclk_monitor_restart_i	std_logic
gt0_rxelecidle_i	std_logic
rx_cdrlock_counter	integer range 0 to WAIT_TIME_CDRLOCK := 0
rx_cdrlocked	std_logic

Instantiations
gtwizard_v2_3_gbe_i	gtwizard_v2_3_gbe <Entity gtwizard_v2_3_gbe>
gt0_txresetfsm_i	gtwizard_v2_3_gbe_TX_STARTUP_FSM <Entity gtwizard_v2_3_gbe_TX_STARTUP_FSM>
gt0_rxresetfsm_i	gtwizard_v2_3_gbe_RX_STARTUP_FSM <Entity gtwizard_v2_3_gbe_RX_STARTUP_FSM>
gt0_rx_recclk_mon_i	gtwizard_v2_3_gbe_RECCLK_MONITOR <Entity gtwizard_v2_3_gbe_RECCLK_MONITOR>
bufg_rxoutclk	bufg
gtwizard_v2_3_gbe_i	gtwizard_v2_3_gbe <Entity gtwizard_v2_3_gbe>
gt0_txresetfsm_i	gtwizard_v2_3_gbe_TX_STARTUP_FSM <Entity gtwizard_v2_3_gbe_TX_STARTUP_FSM>
gt0_rxresetfsm_i	gtwizard_v2_3_gbe_RX_STARTUP_FSM <Entity gtwizard_v2_3_gbe_RX_STARTUP_FSM>
gt0_rx_recclk_mon_i	gtwizard_v2_3_gbe_RECCLK_MONITOR <Entity gtwizard_v2_3_gbe_RECCLK_MONITOR>
bufg_rxoutclk	bufg

Member Function Documentation

cdrlock_timeout() [1/2]

cdrlock_timeout

(

SYSCLK_IN

)

cdrlock_timeout() [2/2]

cdrlock_timeout

(

SYSCLK_IN

)

get_cdrlock_time() [1/2]

integer get_cdrlock_time (   is_sim in in integer   )

Function

get_cdrlock_time() [2/2]

integer get_cdrlock_time (   is_sim in in integer   )

Function

get_lpm_adapt_lock_time() [1/2]

integer get_lpm_adapt_lock_time (   is_sim in in integer   )

Function

get_lpm_adapt_lock_time() [2/2]

integer get_lpm_adapt_lock_time (   is_sim in in integer   )

Function

Member Data Documentation

bufg_rxoutclk [1/2]

bufg_rxoutclk bufg

Instantiation

bufg_rxoutclk [2/2]

bufg_rxoutclk bufg

Instantiation

DFE_ADAPT_LOCK_TIMER

DFE_ADAPT_LOCK_TIMER integer := integer ( ( 13 * 100 ) / integer ( 1 . 25 ) )

Constant

DLY

DLY time := 1 ns

Constant

gt0_adapt_done

gt0_adapt_done std_logic

Signal

gt0_cplllock_i

gt0_cplllock_i std_logic

Signal

gt0_cpllrefclklost_i

gt0_cpllrefclklost_i std_logic

Signal

gt0_cpllreset_i

gt0_cpllreset_i std_logic

Signal

gt0_cpllreset_t

gt0_cpllreset_t std_logic

Signal

gt0_drpaddr_i

gt0_drpaddr_i std_logic_vector ( 8 downto 0 )

Signal

gt0_drpaddr_int

gt0_drpaddr_int std_logic_vector ( 8 downto 0 )

Signal

gt0_drpdi_i

gt0_drpdi_i std_logic_vector ( 15 downto 0 )

Signal

gt0_drpdi_int

gt0_drpdi_int std_logic_vector ( 15 downto 0 )

Signal

gt0_drpdo_int

gt0_drpdo_int std_logic_vector ( 15 downto 0 )

Signal

gt0_drpdo_o

gt0_drpdo_o std_logic_vector ( 15 downto 0 )

Signal

gt0_drpen_i

gt0_drpen_i std_logic

Signal

gt0_drpen_int

gt0_drpen_int std_logic

Signal

gt0_drprdy_int

gt0_drprdy_int std_logic

Signal

gt0_drprdy_o

gt0_drprdy_o std_logic

Signal

gt0_drpwe_i

gt0_drpwe_i std_logic

Signal

gt0_drpwe_int

gt0_drpwe_int std_logic

Signal

gt0_gtrxreset_gt

gt0_gtrxreset_gt std_logic

Signal

gt0_gtrxreset_i

gt0_gtrxreset_i std_logic

Signal

gt0_gtrxreset_t

gt0_gtrxreset_t std_logic

Signal

gt0_gttxreset_gt

gt0_gttxreset_gt std_logic

Signal

gt0_gttxreset_i

gt0_gttxreset_i std_logic

Signal

gt0_gttxreset_t

gt0_gttxreset_t std_logic

Signal

gt0_qplllock_i

gt0_qplllock_i std_logic

Signal

gt0_qpllrefclklost_i

gt0_qpllrefclklost_i std_logic

Signal

gt0_qpllreset_i

gt0_qpllreset_i std_logic

Signal

gt0_qpllreset_t

gt0_qpllreset_t std_logic

Signal

gt0_recclk_mon_i

gt0_recclk_mon_i std_logic

Signal

gt0_recclk_monitor_restart_i

gt0_recclk_monitor_restart_i std_logic

Signal

gt0_recclk_stable_i

gt0_recclk_stable_i std_logic

Signal

gt0_rx_recclk_mon_i [1/2]

gt0_rx_recclk_mon_i gtwizard_v2_3_gbe_RECCLK_MONITOR

Instantiation

gt0_rx_recclk_mon_i [2/2]

gt0_rx_recclk_mon_i gtwizard_v2_3_gbe_RECCLK_MONITOR

Instantiation

gt0_rxdfeagchold_i

gt0_rxdfeagchold_i std_logic

Signal

gt0_rxdfelfhold_i

gt0_rxdfelfhold_i std_logic

Signal

gt0_rxdfelpmreset_i

gt0_rxdfelpmreset_i std_logic

Signal

gt0_rxelecidle_i

gt0_rxelecidle_i std_logic

Signal

gt0_rxlpmhfhold_i

gt0_rxlpmhfhold_i std_logic

Signal

gt0_rxlpmlfhold_i

gt0_rxlpmlfhold_i std_logic

Signal

gt0_rxmonitorout_o

gt0_rxmonitorout_o std_logic_vector ( 6 downto 0 )

Signal

gt0_rxmonitorsel_i

gt0_rxmonitorsel_i std_logic_vector ( 1 downto 0 )

Signal

gt0_rxoutclk_i

gt0_rxoutclk_i std_logic

Signal

gt0_rxoutclk_i_buf

gt0_rxoutclk_i_buf std_logic

Signal

gt0_rxpcsreset_i

gt0_rxpcsreset_i std_logic

Signal

gt0_rxpmareset_i

gt0_rxpmareset_i std_logic

Signal

gt0_rxresetdone_i

gt0_rxresetdone_i std_logic

Signal

gt0_rxresetfsm_i [1/2]

gt0_rxresetfsm_i gtwizard_v2_3_gbe_RX_STARTUP_FSM

Instantiation

gt0_rxresetfsm_i [2/2]

gt0_rxresetfsm_i gtwizard_v2_3_gbe_RX_STARTUP_FSM

Instantiation

gt0_rxuserrdy_i

gt0_rxuserrdy_i std_logic

Signal

gt0_rxuserrdy_t

gt0_rxuserrdy_t std_logic

Signal

gt0_txpcsreset_i

gt0_txpcsreset_i std_logic

Signal

gt0_txresetdone_i

gt0_txresetdone_i std_logic

Signal

gt0_txresetfsm_i [1/2]

gt0_txresetfsm_i gtwizard_v2_3_gbe_TX_STARTUP_FSM

Instantiation

gt0_txresetfsm_i [2/2]

gt0_txresetfsm_i gtwizard_v2_3_gbe_TX_STARTUP_FSM

Instantiation

gt0_txuserrdy_i

gt0_txuserrdy_i std_logic

Signal

gt0_txuserrdy_t

gt0_txuserrdy_t std_logic

Signal

gtwizard_v2_3_gbe

gtwizard_v2_3_gbe

Component

gtwizard_v2_3_gbe_i [1/2]

gtwizard_v2_3_gbe_i gtwizard_v2_3_gbe

Instantiation

gtwizard_v2_3_gbe_i [2/2]

gtwizard_v2_3_gbe_i gtwizard_v2_3_gbe

Instantiation

gtwizard_v2_3_gbe_RECCLK_MONITOR

gtwizard_v2_3_gbe_RECCLK_MONITOR

Component

gtwizard_v2_3_gbe_RX_STARTUP_FSM

gtwizard_v2_3_gbe_RX_STARTUP_FSM

Component

gtwizard_v2_3_gbe_TX_STARTUP_FSM

gtwizard_v2_3_gbe_TX_STARTUP_FSM

Component

LPM_ADAPT_LOCK_TIMER

LPM_ADAPT_LOCK_TIMER integer := get_lpm_adapt_lock_time ( EXAMPLE_SIMULATION )

Constant

rx_cdrlock_counter

rx_cdrlock_counter integer range 0 to WAIT_TIME_CDRLOCK := 0

Signal

RX_CDRLOCK_TIME

RX_CDRLOCK_TIME integer := get_cdrlock_time ( EXAMPLE_SIMULATION )

Constant

rx_cdrlocked

rx_cdrlocked std_logic

Signal

STABLE_CLOCK_PERIOD

STABLE_CLOCK_PERIOD integer := 8

Constant

tied_to_ground_i

tied_to_ground_i std_logic

Signal

tied_to_vcc_i

tied_to_vcc_i std_logic

Signal

WAIT_TIME_CDRLOCK

WAIT_TIME_CDRLOCK integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD

Constant

---

The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/gtwizard_v2_3_gbe/gtwizard_v2_3_gbe_init.vhd