gtwizard_v2_5_gbe_gth_GT Entity Reference

Inheritance diagram for gtwizard_v2_5_gbe_gth_GT:

Collaboration diagram for gtwizard_v2_5_gbe_gth_GT:

Entities
RTL	architecture

Libraries
ieee
UNISIM

Use Clauses
std_logic_1164
numeric_std
VCOMPONENTS

Generics
GT_SIM_GTRESET_SPEEDUP	string := " FALSE "
EXAMPLE_SIMULATION	integer := 0
TXSYNC_OVRD_IN	bit := ' 0 '
TXSYNC_MULTILANE_IN	bit := ' 0 '

Ports
RST_IN	in std_logic
DRP_BUSY_OUT	out std_logic
CPLLFBCLKLOST_OUT	out std_logic
CPLLLOCK_OUT	out std_logic
CPLLLOCKDETCLK_IN	in std_logic
CPLLREFCLKLOST_OUT	out std_logic
CPLLRESET_IN	in std_logic
GTREFCLK0_IN	in std_logic
DRPADDR_IN	in std_logic_vector ( 8 downto 0 )
DRPCLK_IN	in std_logic
DRPDI_IN	in std_logic_vector ( 15 downto 0 )
DRPDO_OUT	out std_logic_vector ( 15 downto 0 )
DRPEN_IN	in std_logic
DRPRDY_OUT	out std_logic
DRPWE_IN	in std_logic
QPLLCLK_IN	in std_logic
QPLLREFCLK_IN	in std_logic
LOOPBACK_IN	in std_logic_vector ( 2 downto 0 )
RXPD_IN	in std_logic_vector ( 1 downto 0 )
TXPD_IN	in std_logic_vector ( 1 downto 0 )
RXUSERRDY_IN	in std_logic
EYESCANDATAERROR_OUT	out std_logic
RXCDRLOCK_OUT	out std_logic
RXCLKCORCNT_OUT	out std_logic_vector ( 1 downto 0 )
RXUSRCLK_IN	in std_logic
RXUSRCLK2_IN	in std_logic
RXDATA_OUT	out std_logic_vector ( 15 downto 0 )
RXDISPERR_OUT	out std_logic_vector ( 1 downto 0 )
RXNOTINTABLE_OUT	out std_logic_vector ( 1 downto 0 )
GTHRXN_IN	in std_logic
RXBUFRESET_IN	in std_logic
RXBUFSTATUS_OUT	out std_logic_vector ( 2 downto 0 )
RXMCOMMAALIGNEN_IN	in std_logic
RXPCOMMAALIGNEN_IN	in std_logic
RXLPMHFHOLD_IN	in std_logic
RXLPMLFHOLD_IN	in std_logic
RXOUTCLK_OUT	out std_logic
GTRXRESET_IN	in std_logic
RXPCSRESET_IN	in std_logic
RXCHARISCOMMA_OUT	out std_logic_vector ( 1 downto 0 )
RXCHARISK_OUT	out std_logic_vector ( 1 downto 0 )
GTHRXP_IN	in std_logic
RXRESETDONE_OUT	out std_logic
GTTXRESET_IN	in std_logic
TXUSERRDY_IN	in std_logic
TXCHARDISPMODE_IN	in std_logic_vector ( 1 downto 0 )
TXCHARDISPVAL_IN	in std_logic_vector ( 1 downto 0 )
TXUSRCLK_IN	in std_logic
TXUSRCLK2_IN	in std_logic
TXELECIDLE_IN	in std_logic
TXBUFSTATUS_OUT	out std_logic_vector ( 1 downto 0 )
TXDATA_IN	in std_logic_vector ( 15 downto 0 )
GTHTXN_OUT	out std_logic
GTHTXP_OUT	out std_logic
TXOUTCLK_OUT	out std_logic
TXOUTCLKFABRIC_OUT	out std_logic
TXOUTCLKPCS_OUT	out std_logic
TXPCSRESET_IN	in std_logic
TXRESETDONE_OUT	out std_logic
TXCHARISK_IN	in std_logic_vector ( 1 downto 0 )

Member Data Documentation

CPLLFBCLKLOST_OUT

CPLLFBCLKLOST_OUT out std_logic

Port

CPLLLOCK_OUT

CPLLLOCK_OUT out std_logic

Port

CPLLLOCKDETCLK_IN

CPLLLOCKDETCLK_IN in std_logic

Port

CPLLREFCLKLOST_OUT

CPLLREFCLKLOST_OUT out std_logic

Port

CPLLRESET_IN

CPLLRESET_IN in std_logic

Port

DRP_BUSY_OUT

DRP_BUSY_OUT out std_logic

Port

DRPADDR_IN

DRPADDR_IN in std_logic_vector ( 8 downto 0 )

Port

DRPCLK_IN

DRPCLK_IN in std_logic

Port

DRPDI_IN

DRPDI_IN in std_logic_vector ( 15 downto 0 )

Port

DRPDO_OUT

DRPDO_OUT out std_logic_vector ( 15 downto 0 )

Port

DRPEN_IN

DRPEN_IN in std_logic

Port

DRPRDY_OUT

DRPRDY_OUT out std_logic

Port

DRPWE_IN

DRPWE_IN in std_logic

Port

EXAMPLE_SIMULATION

EXAMPLE_SIMULATION integer := 0

Generic

EYESCANDATAERROR_OUT

EYESCANDATAERROR_OUT out std_logic

Port

GT_SIM_GTRESET_SPEEDUP

GT_SIM_GTRESET_SPEEDUP string := " FALSE "

Generic

GTHRXN_IN

GTHRXN_IN in std_logic

Port

GTHRXP_IN

GTHRXP_IN in std_logic

Port

GTHTXN_OUT

GTHTXN_OUT out std_logic

Port

GTHTXP_OUT

GTHTXP_OUT out std_logic

Port

GTREFCLK0_IN

GTREFCLK0_IN in std_logic

Port

GTRXRESET_IN

GTRXRESET_IN in std_logic

Port

GTTXRESET_IN

GTTXRESET_IN in std_logic

Port

ieee

ieee

Library

LOOPBACK_IN

LOOPBACK_IN in std_logic_vector ( 2 downto 0 )

Port

numeric_std

numeric_std

Package

QPLLCLK_IN

QPLLCLK_IN in std_logic

Port

QPLLREFCLK_IN

QPLLREFCLK_IN in std_logic

Port

RST_IN

RST_IN in std_logic

Port

RXBUFRESET_IN

RXBUFRESET_IN in std_logic

Port

RXBUFSTATUS_OUT

RXBUFSTATUS_OUT out std_logic_vector ( 2 downto 0 )

Port

RXCDRLOCK_OUT

RXCDRLOCK_OUT out std_logic

Port

RXCHARISCOMMA_OUT

RXCHARISCOMMA_OUT out std_logic_vector ( 1 downto 0 )

Port

RXCHARISK_OUT

RXCHARISK_OUT out std_logic_vector ( 1 downto 0 )

Port

RXCLKCORCNT_OUT

RXCLKCORCNT_OUT out std_logic_vector ( 1 downto 0 )

Port

RXDATA_OUT

RXDATA_OUT out std_logic_vector ( 15 downto 0 )

Port

RXDISPERR_OUT

RXDISPERR_OUT out std_logic_vector ( 1 downto 0 )

Port

RXLPMHFHOLD_IN

RXLPMHFHOLD_IN in std_logic

Port

RXLPMLFHOLD_IN

RXLPMLFHOLD_IN in std_logic

Port

RXMCOMMAALIGNEN_IN

RXMCOMMAALIGNEN_IN in std_logic

Port

RXNOTINTABLE_OUT

RXNOTINTABLE_OUT out std_logic_vector ( 1 downto 0 )

Port

RXOUTCLK_OUT

RXOUTCLK_OUT out std_logic

Port

RXPCOMMAALIGNEN_IN

RXPCOMMAALIGNEN_IN in std_logic

Port

RXPCSRESET_IN

RXPCSRESET_IN in std_logic

Port

RXPD_IN

RXPD_IN in std_logic_vector ( 1 downto 0 )

Port

RXRESETDONE_OUT

RXRESETDONE_OUT out std_logic

Port

RXUSERRDY_IN

RXUSERRDY_IN in std_logic

Port

RXUSRCLK2_IN

RXUSRCLK2_IN in std_logic

Port

RXUSRCLK_IN

RXUSRCLK_IN in std_logic

Port

std_logic_1164

std_logic_1164

Package

TXBUFSTATUS_OUT

TXBUFSTATUS_OUT out std_logic_vector ( 1 downto 0 )

Port

TXCHARDISPMODE_IN

TXCHARDISPMODE_IN in std_logic_vector ( 1 downto 0 )

Port

TXCHARDISPVAL_IN

TXCHARDISPVAL_IN in std_logic_vector ( 1 downto 0 )

Port

TXCHARISK_IN

TXCHARISK_IN in std_logic_vector ( 1 downto 0 )

Port

TXDATA_IN

TXDATA_IN in std_logic_vector ( 15 downto 0 )

Port

TXELECIDLE_IN

TXELECIDLE_IN in std_logic

Port

TXOUTCLK_OUT

TXOUTCLK_OUT out std_logic

Port

TXOUTCLKFABRIC_OUT

TXOUTCLKFABRIC_OUT out std_logic

Port

TXOUTCLKPCS_OUT

TXOUTCLKPCS_OUT out std_logic

Port

TXPCSRESET_IN

TXPCSRESET_IN in std_logic

Port

TXPD_IN

TXPD_IN in std_logic_vector ( 1 downto 0 )

Port

TXRESETDONE_OUT

TXRESETDONE_OUT out std_logic

Port

TXSYNC_MULTILANE_IN

TXSYNC_MULTILANE_IN bit := ' 0 '

Generic

TXSYNC_OVRD_IN

TXSYNC_OVRD_IN bit := ' 0 '

Generic

TXUSERRDY_IN

TXUSERRDY_IN in std_logic

Port

TXUSRCLK2_IN

TXUSRCLK2_IN in std_logic

Port

TXUSRCLK_IN

TXUSRCLK_IN in std_logic

Port

UNISIM

UNISIM

Library

VCOMPONENTS

VCOMPONENTS

Package

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/gtwizard_v2_5_gbe_gth/gtwizard_v2_5_gbe_gth_gt.vhd