RTL Architecture Reference

Processes
PROCESS_247	( DRPCLK_IN )
PROCESS_248	( DRPCLK_IN )
PROCESS_808	( DRPCLK_IN )
PROCESS_809	( DRPCLK_IN )

Components
gtwizard_v2_5_gbe_gth_gtrxreset_seq	<Entity gtwizard_v2_5_gbe_gth_gtrxreset_seq>
gtwizard_v2_5_gbe_gth_rxpmarst_seq	<Entity gtwizard_v2_5_gbe_gth_rxpmarst_seq>
gtwizard_v2_5_gbe_gth_rxrate_seq	<Entity gtwizard_v2_5_gbe_gth_rxrate_seq>

Signals
tied_to_ground_i	std_logic
tied_to_ground_vec_i	std_logic_vector ( 63 downto 0 )
tied_to_vcc_i	std_logic
rxpmaresetdone_t	std_logic
gtrxreset_out	std_logic
rxpmareset_out	std_logic
rxrate_out	std_logic_vector ( 2 downto 0 )
drp_op_done	std_logic
drp_pma_busy	std_logic
drp_rate_busy	std_logic
drp_busy_i1	std_logic := ' 0 '
drp_busy_i2	std_logic := ' 0 '
drpen_rst_t	std_logic
drpaddr_rst_t	std_logic_vector ( 8 downto 0 )
drpwe_rst_t	std_logic
drpdo_rst_t	std_logic_vector ( 15 downto 0 )
drpdi_rst_t	std_logic_vector ( 15 downto 0 )
drprdy_rst_t	std_logic
drpen_pma_t	std_logic
drpaddr_pma_t	std_logic_vector ( 8 downto 0 )
drpwe_pma_t	std_logic
drpdo_pma_t	std_logic_vector ( 15 downto 0 )
drpdi_pma_t	std_logic_vector ( 15 downto 0 )
drprdy_pma_t	std_logic
drpen_rate_t	std_logic
drpaddr_rate_t	std_logic_vector ( 8 downto 0 )
drpwe_rate_t	std_logic
drpdo_rate_t	std_logic_vector ( 15 downto 0 )
drpdi_rate_t	std_logic_vector ( 15 downto 0 )
drprdy_rate_t	std_logic
drpen_i	std_logic
drpaddr_i	std_logic_vector ( 8 downto 0 )
drpwe_i	std_logic
drpdo_i	std_logic_vector ( 15 downto 0 )
drpdi_i	std_logic_vector ( 15 downto 0 )
drprdy_i	std_logic
rxdata_i	std_logic_vector ( 63 downto 0 )
rxchariscomma_float_i	std_logic_vector ( 5 downto 0 )
rxcharisk_float_i	std_logic_vector ( 5 downto 0 )
rxdisperr_float_i	std_logic_vector ( 5 downto 0 )
rxnotintable_float_i	std_logic_vector ( 5 downto 0 )
rxrundisp_float_i	std_logic_vector ( 5 downto 0 )
txdata_i	std_logic_vector ( 63 downto 0 )
txkerr_float_i	std_logic_vector ( 5 downto 0 )
txrundisp_float_i	std_logic_vector ( 5 downto 0 )

Instantiations
gthe2_i	gthe2_channel
gtrxreset_seq_i	gtwizard_v2_5_gbe_gth_gtrxreset_seq <Entity gtwizard_v2_5_gbe_gth_gtrxreset_seq>
gthe2_i	gthe2_channel
gtrxreset_seq_i	gtwizard_v2_5_gbe_gth_gtrxreset_seq <Entity gtwizard_v2_5_gbe_gth_gtrxreset_seq>

Member Function Documentation

PROCESS_247()

PROCESS_247

(

DRPCLK_IN

)

PROCESS_248()

PROCESS_248 (   DRPCLK_IN   )

Process

PROCESS_808()

PROCESS_808

(

DRPCLK_IN

)

PROCESS_809()

PROCESS_809 (   DRPCLK_IN   )

Process

Member Data Documentation

drp_busy_i1

drp_busy_i1 std_logic := ' 0 '

Signal

drp_busy_i2

drp_busy_i2 std_logic := ' 0 '

Signal

drp_op_done

drp_op_done std_logic

Signal

drp_pma_busy

drp_pma_busy std_logic

Signal

drp_rate_busy

drp_rate_busy std_logic

Signal

drpaddr_i

drpaddr_i std_logic_vector ( 8 downto 0 )

Signal

drpaddr_pma_t

drpaddr_pma_t std_logic_vector ( 8 downto 0 )

Signal

drpaddr_rate_t

drpaddr_rate_t std_logic_vector ( 8 downto 0 )

Signal

drpaddr_rst_t

drpaddr_rst_t std_logic_vector ( 8 downto 0 )

Signal

drpdi_i

drpdi_i std_logic_vector ( 15 downto 0 )

Signal

drpdi_pma_t

drpdi_pma_t std_logic_vector ( 15 downto 0 )

Signal

drpdi_rate_t

drpdi_rate_t std_logic_vector ( 15 downto 0 )

Signal

drpdi_rst_t

drpdi_rst_t std_logic_vector ( 15 downto 0 )

Signal

drpdo_i

drpdo_i std_logic_vector ( 15 downto 0 )

Signal

drpdo_pma_t

drpdo_pma_t std_logic_vector ( 15 downto 0 )

Signal

drpdo_rate_t

drpdo_rate_t std_logic_vector ( 15 downto 0 )

Signal

drpdo_rst_t

drpdo_rst_t std_logic_vector ( 15 downto 0 )

Signal

drpen_i

drpen_i std_logic

Signal

drpen_pma_t

drpen_pma_t std_logic

Signal

drpen_rate_t

drpen_rate_t std_logic

Signal

drpen_rst_t

drpen_rst_t std_logic

Signal

drprdy_i

drprdy_i std_logic

Signal

drprdy_pma_t

drprdy_pma_t std_logic

Signal

drprdy_rate_t

drprdy_rate_t std_logic

Signal

drprdy_rst_t

drprdy_rst_t std_logic

Signal

drpwe_i

drpwe_i std_logic

Signal

drpwe_pma_t

drpwe_pma_t std_logic

Signal

drpwe_rate_t

drpwe_rate_t std_logic

Signal

drpwe_rst_t

drpwe_rst_t std_logic

Signal

gthe2_i [1/2]

gthe2_i gthe2_channel

Instantiation

gthe2_i [2/2]

gthe2_i gthe2_channel

Instantiation

gtrxreset_out

gtrxreset_out std_logic

Signal

gtrxreset_seq_i [1/2]

gtrxreset_seq_i gtwizard_v2_5_gbe_gth_gtrxreset_seq

Instantiation

gtrxreset_seq_i [2/2]

gtrxreset_seq_i gtwizard_v2_5_gbe_gth_gtrxreset_seq

Instantiation

gtwizard_v2_5_gbe_gth_gtrxreset_seq

gtwizard_v2_5_gbe_gth_gtrxreset_seq

Component

gtwizard_v2_5_gbe_gth_rxpmarst_seq

gtwizard_v2_5_gbe_gth_rxpmarst_seq

Component

gtwizard_v2_5_gbe_gth_rxrate_seq

gtwizard_v2_5_gbe_gth_rxrate_seq

Component

rxchariscomma_float_i

rxchariscomma_float_i std_logic_vector ( 5 downto 0 )

Signal

rxcharisk_float_i

rxcharisk_float_i std_logic_vector ( 5 downto 0 )

Signal

rxdata_i

rxdata_i std_logic_vector ( 63 downto 0 )

Signal

rxdisperr_float_i

rxdisperr_float_i std_logic_vector ( 5 downto 0 )

Signal

rxnotintable_float_i

rxnotintable_float_i std_logic_vector ( 5 downto 0 )

Signal

rxpmareset_out

rxpmareset_out std_logic

Signal

rxpmaresetdone_t

rxpmaresetdone_t std_logic

Signal

rxrate_out

rxrate_out std_logic_vector ( 2 downto 0 )

Signal

rxrundisp_float_i

rxrundisp_float_i std_logic_vector ( 5 downto 0 )

Signal

tied_to_ground_i

tied_to_ground_i std_logic

Signal

tied_to_ground_vec_i

tied_to_ground_vec_i std_logic_vector ( 63 downto 0 )

Signal

tied_to_vcc_i

tied_to_vcc_i std_logic

Signal

txdata_i

txdata_i std_logic_vector ( 63 downto 0 )

Signal

txkerr_float_i

txkerr_float_i std_logic_vector ( 5 downto 0 )

Signal

txrundisp_float_i

txrundisp_float_i std_logic_vector ( 5 downto 0 )

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/gtwizard_v2_5_gbe_gth/gtwizard_v2_5_gbe_gth_gt.vhd