My Project  v0.0.16
Constants | Components | Signals | Processes | Procedures | Instantiations
RTL Architecture Reference

Processes

PROCESS_233  ( )
PROCESS_234  ( )
PROCESS_235  ( )
PROCESS_236  ( )
PROCESS_237  ( )
PROCESS_238  ( )
PROCESS_239  ( )
PROCESS_794  ( )
PROCESS_795  ( )
PROCESS_796  ( )
PROCESS_797  ( )
PROCESS_798  ( )
PROCESS_799  ( )
PROCESS_800  ( )

Procedures

  tbprint( message: in string )
  tbprint( message: in string )

Components

gtwizard_v2_5_gbe_gth_exdes  <Entity gtwizard_v2_5_gbe_gth_exdes>
SIM_RESET_GT_MODEL  <Entity SIM_RESET_GT_MODEL>

Constants

TX_REFCLK_PERIOD  time := 8 . 0 ns
RX_REFCLK_PERIOD  time := 8 . 0 ns
SYSCLK_PERIOD  time := 20 ns
DCLK_PERIOD  time := 20 . 0 ns

Signals

tx_refclk_n_r  std_logic
rx_refclk_n_r  std_logic
drp_clk_r  std_logic
sysclk_r  std_logic
tx_usrclk_r  std_logic
rx_usrclk_r  std_logic
gsr_r  std_logic
gts_r  std_logic
gttx_reset_i  std_logic
gtrx_reset_i  std_logic
cpll_reset_i  std_logic
qpll_reset_i  std_logic
reset_i  std_logic
track_data_high_r  std_logic
track_data_low_r  std_logic
tx_refclk_p_r  std_logic
rx_refclk_p_r  std_logic
tied_to_ground_i  std_logic
rxn_in_i  std_logic
rxp_in_i  std_logic
txn_out_i  std_logic
txp_out_i  std_logic
gt0_txplllkdet_i  std_logic
gt0_rxplllkdet_i  std_logic
track_data_i  std_logic

Instantiations

sim_reset_mgt_model_i  SIM_RESET_GT_MODEL <Entity SIM_RESET_GT_MODEL>
gtwizard_v2_5_gbe_gth_exdes_i  gtwizard_v2_5_gbe_gth_exdes <Entity gtwizard_v2_5_gbe_gth_exdes>
sim_reset_mgt_model_i  SIM_RESET_GT_MODEL <Entity SIM_RESET_GT_MODEL>
gtwizard_v2_5_gbe_gth_exdes_i  gtwizard_v2_5_gbe_gth_exdes <Entity gtwizard_v2_5_gbe_gth_exdes>

Member Function Documentation

◆ PROCESS_233()

PROCESS_233 ( )

◆ PROCESS_234()

PROCESS_234 ( )
Process

◆ PROCESS_235()

PROCESS_235 ( )
Process

◆ PROCESS_236()

PROCESS_236 ( )
Process

◆ PROCESS_237()

PROCESS_237 ( )
Process

◆ PROCESS_238()

PROCESS_238 ( )
Process

◆ PROCESS_239()

PROCESS_239 ( )
Process

◆ PROCESS_794()

PROCESS_794 ( )

◆ PROCESS_795()

PROCESS_795 ( )
Process

◆ PROCESS_796()

PROCESS_796 ( )
Process

◆ PROCESS_797()

PROCESS_797 ( )
Process

◆ PROCESS_798()

PROCESS_798 ( )
Process

◆ PROCESS_799()

PROCESS_799 ( )
Process

◆ PROCESS_800()

PROCESS_800 ( )
Process

◆ tbprint() [1/2]

tbprint (   message in string  
)
Procedure

◆ tbprint() [2/2]

tbprint (   message in string  
)
Procedure

Member Data Documentation

◆ cpll_reset_i

cpll_reset_i std_logic
Signal

◆ DCLK_PERIOD

DCLK_PERIOD time := 20 . 0 ns
Constant

◆ drp_clk_r

drp_clk_r std_logic
Signal

◆ gsr_r

gsr_r std_logic
Signal

◆ gt0_rxplllkdet_i

gt0_rxplllkdet_i std_logic
Signal

◆ gt0_txplllkdet_i

gt0_txplllkdet_i std_logic
Signal

◆ gtrx_reset_i

gtrx_reset_i std_logic
Signal

◆ gts_r

gts_r std_logic
Signal

◆ gttx_reset_i

gttx_reset_i std_logic
Signal

◆ gtwizard_v2_5_gbe_gth_exdes

◆ gtwizard_v2_5_gbe_gth_exdes_i [1/2]

gtwizard_v2_5_gbe_gth_exdes_i gtwizard_v2_5_gbe_gth_exdes
Instantiation

◆ gtwizard_v2_5_gbe_gth_exdes_i [2/2]

gtwizard_v2_5_gbe_gth_exdes_i gtwizard_v2_5_gbe_gth_exdes
Instantiation

◆ qpll_reset_i

qpll_reset_i std_logic
Signal

◆ reset_i

reset_i std_logic
Signal

◆ rx_refclk_n_r

rx_refclk_n_r std_logic
Signal

◆ rx_refclk_p_r

rx_refclk_p_r std_logic
Signal

◆ RX_REFCLK_PERIOD

RX_REFCLK_PERIOD time := 8 . 0 ns
Constant

◆ rx_usrclk_r

rx_usrclk_r std_logic
Signal

◆ rxn_in_i

rxn_in_i std_logic
Signal

◆ rxp_in_i

rxp_in_i std_logic
Signal

◆ SIM_RESET_GT_MODEL

SIM_RESET_GT_MODEL
Component

◆ sim_reset_mgt_model_i [1/2]

sim_reset_mgt_model_i SIM_RESET_GT_MODEL
Instantiation

◆ sim_reset_mgt_model_i [2/2]

sim_reset_mgt_model_i SIM_RESET_GT_MODEL
Instantiation

◆ SYSCLK_PERIOD

SYSCLK_PERIOD time := 20 ns
Constant

◆ sysclk_r

sysclk_r std_logic
Signal

◆ tied_to_ground_i

tied_to_ground_i std_logic
Signal

◆ track_data_high_r

track_data_high_r std_logic
Signal

◆ track_data_i

track_data_i std_logic
Signal

◆ track_data_low_r

track_data_low_r std_logic
Signal

◆ tx_refclk_n_r

tx_refclk_n_r std_logic
Signal

◆ tx_refclk_p_r

tx_refclk_p_r std_logic
Signal

◆ TX_REFCLK_PERIOD

TX_REFCLK_PERIOD time := 8 . 0 ns
Constant

◆ tx_usrclk_r

tx_usrclk_r std_logic
Signal

◆ txn_out_i

txn_out_i std_logic
Signal

◆ txp_out_i

txp_out_i std_logic
Signal

The documentation for this class was generated from the following file: