gtwizard_v2_5_gbe_gth_exdes Entity Reference

Inheritance diagram for gtwizard_v2_5_gbe_gth_exdes:

Collaboration diagram for gtwizard_v2_5_gbe_gth_exdes:

Entities
RTL	architecture

Libraries
ieee
UNISIM

Use Clauses
std_logic_1164
numeric_std
VCOMPONENTS

Generics
EXAMPLE_CONFIG_INDEPENDENT_LANES	integer := 1
EXAMPLE_LANE_WITH_START_CHAR	integer := 0
EXAMPLE_WORDS_IN_BRAM	integer := 512
EXAMPLE_SIM_GTRESET_SPEEDUP	string := " TRUE "
EXAMPLE_SIMULATION	integer := 0
EXAMPLE_USE_CHIPSCOPE	integer := 0

Ports
Q9_CLK0_GTREFCLK_PAD_N_IN	in std_logic
Q9_CLK0_GTREFCLK_PAD_P_IN	in std_logic
DRP_CLK_IN	in std_logic
SYSCLK_IN	in std_logic
GTTX_RESET_IN	in std_logic
GTRX_RESET_IN	in std_logic
CPLL_RESET_IN	in std_logic
QPLL_RESET_IN	in std_logic
TRACK_DATA_OUT	out std_logic
RXN_IN	in std_logic
RXP_IN	in std_logic
TXN_OUT	out std_logic
TXP_OUT	out std_logic

Member Data Documentation

CPLL_RESET_IN

CPLL_RESET_IN in std_logic

Port

DRP_CLK_IN

DRP_CLK_IN in std_logic

Port

EXAMPLE_CONFIG_INDEPENDENT_LANES

EXAMPLE_CONFIG_INDEPENDENT_LANES integer := 1

Generic

EXAMPLE_LANE_WITH_START_CHAR

EXAMPLE_LANE_WITH_START_CHAR integer := 0

Generic

EXAMPLE_SIM_GTRESET_SPEEDUP

EXAMPLE_SIM_GTRESET_SPEEDUP string := " TRUE "

Generic

EXAMPLE_SIMULATION

EXAMPLE_SIMULATION integer := 0

Generic

EXAMPLE_USE_CHIPSCOPE

EXAMPLE_USE_CHIPSCOPE integer := 0

Generic

EXAMPLE_WORDS_IN_BRAM

EXAMPLE_WORDS_IN_BRAM integer := 512

Generic

GTRX_RESET_IN

GTRX_RESET_IN in std_logic

Port

GTTX_RESET_IN

GTTX_RESET_IN in std_logic

Port

ieee

ieee

Library

numeric_std

numeric_std

Package

Q9_CLK0_GTREFCLK_PAD_N_IN

Q9_CLK0_GTREFCLK_PAD_N_IN in std_logic

Port

Q9_CLK0_GTREFCLK_PAD_P_IN

Q9_CLK0_GTREFCLK_PAD_P_IN in std_logic

Port

QPLL_RESET_IN

QPLL_RESET_IN in std_logic

Port

RXN_IN

RXN_IN in std_logic

Port

RXP_IN

RXP_IN in std_logic

Port

std_logic_1164

std_logic_1164

Package

SYSCLK_IN

SYSCLK_IN in std_logic

Port

TRACK_DATA_OUT

TRACK_DATA_OUT out std_logic

Port

TXN_OUT

TXN_OUT out std_logic

Port

TXP_OUT

TXP_OUT out std_logic

Port

UNISIM

UNISIM

Library

VCOMPONENTS

VCOMPONENTS

Package

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/gtwizard_v2_5_gbe_gth/gtwizard_v2_5_gbe_gth/example_design/gtwizard_v2_5_gbe_gth_exdes.vhd