RTL Architecture Reference

Collaboration diagram for RTL:

Functions
std_logic	and_reduce ( arg: in std_logic_vector )
std_logic	and_reduce ( arg: in std_logic_vector )

Processes
PROCESS_177	( gt0_rxusrclk_i , gt0_rxresetdone_i )
PROCESS_178	( gt0_txusrclk_i , gt0_txfsmresetdone_i )
PROCESS_738	( gt0_rxusrclk_i , gt0_rxresetdone_i )
PROCESS_739	( gt0_txusrclk_i , gt0_txfsmresetdone_i )

Components
gtwizard_v2_5_gbe_gth_init	<Entity gtwizard_v2_5_gbe_gth_init>
gtwizard_v2_5_gbe_gth_GT_USRCLK_SOURCE	<Entity gtwizard_v2_5_gbe_gth_GT_USRCLK_SOURCE>
gtwizard_v2_5_gbe_gth_GT_FRAME_GEN	<Entity gtwizard_v2_5_gbe_gth_GT_FRAME_GEN>
gtwizard_v2_5_gbe_gth_GT_FRAME_CHECK	<Entity gtwizard_v2_5_gbe_gth_GT_FRAME_CHECK>
data_vio
icon
ila

Constants
DLY	time := 1 ns

Signals
gt0_txfsmresetdone_i	std_logic
gt0_rxfsmresetdone_i	std_logic
gt0_txfsmresetdone_r	std_logic
gt0_txfsmresetdone_r2	std_logic
gt0_rxresetdone_r	std_logic
gt0_rxresetdone_r2	std_logic
gt0_rxresetdone_r3	std_logic
gt0_cpllfbclklost_i	std_logic
gt0_cplllock_i	std_logic
gt0_cpllrefclklost_i	std_logic
gt0_cpllreset_i	std_logic
gt0_drpaddr_i	std_logic_vector ( 8 downto 0 )
gt0_drpdi_i	std_logic_vector ( 15 downto 0 )
gt0_drpdo_i	std_logic_vector ( 15 downto 0 )
gt0_drpen_i	std_logic
gt0_drprdy_i	std_logic
gt0_drpwe_i	std_logic
gt0_loopback_i	std_logic_vector ( 2 downto 0 )
gt0_rxpd_i	std_logic_vector ( 1 downto 0 )
gt0_txpd_i	std_logic_vector ( 1 downto 0 )
gt0_rxuserrdy_i	std_logic
gt0_eyescandataerror_i	std_logic
gt0_rxcdrlock_i	std_logic
gt0_rxclkcorcnt_i	std_logic_vector ( 1 downto 0 )
gt0_rxdata_i	std_logic_vector ( 15 downto 0 )
gt0_rxdisperr_i	std_logic_vector ( 1 downto 0 )
gt0_rxnotintable_i	std_logic_vector ( 1 downto 0 )
gt0_gthrxn_i	std_logic
gt0_rxbufreset_i	std_logic
gt0_rxbufstatus_i	std_logic_vector ( 2 downto 0 )
gt0_rxmcommaalignen_i	std_logic
gt0_rxpcommaalignen_i	std_logic
gt0_rxoutclk_i	std_logic
gt0_gtrxreset_i	std_logic
gt0_rxpcsreset_i	std_logic
gt0_rxchariscomma_i	std_logic_vector ( 1 downto 0 )
gt0_rxcharisk_i	std_logic_vector ( 1 downto 0 )
gt0_gthrxp_i	std_logic
gt0_rxresetdone_i	std_logic
gt0_gttxreset_i	std_logic
gt0_txuserrdy_i	std_logic
gt0_txchardispmode_i	std_logic_vector ( 1 downto 0 )
gt0_txchardispval_i	std_logic_vector ( 1 downto 0 )
gt0_txelecidle_i	std_logic
gt0_txbufstatus_i	std_logic_vector ( 1 downto 0 )
gt0_txdata_i	std_logic_vector ( 15 downto 0 )
gt0_gthtxn_i	std_logic
gt0_gthtxp_i	std_logic
gt0_txoutclk_i	std_logic
gt0_txoutclkfabric_i	std_logic
gt0_txoutclkpcs_i	std_logic
gt0_txpcsreset_i	std_logic
gt0_txresetdone_i	std_logic
gt0_txcharisk_i	std_logic_vector ( 1 downto 0 )
gt0_qplllock_i	std_logic
gt0_qpllrefclklost_i	std_logic
gt0_qpllreset_i	std_logic
gt0_tx_system_reset_c	std_logic
gt0_rx_system_reset_c	std_logic
tied_to_ground_i	std_logic
tied_to_ground_vec_i	std_logic_vector ( 63 downto 0 )
tied_to_vcc_i	std_logic
tied_to_vcc_vec_i	std_logic_vector ( 7 downto 0 )
drpclk_in_i	std_logic
GTTXRESET_IN	std_logic
GTRXRESET_IN	std_logic
CPLLRESET_IN	std_logic
QPLLRESET_IN	std_logic
gt0_txusrclk_i	std_logic
gt0_txusrclk2_i	std_logic
gt0_rxusrclk_i	std_logic
gt0_rxusrclk2_i	std_logic
q9_clk0_refclk_i	std_logic
gt0_matchn_i	std_logic
gt0_txcharisk_float_i	std_logic_vector ( 5 downto 0 )
gt0_txdata_float16_i	std_logic_vector ( 15 downto 0 )
gt0_txdata_float_i	std_logic_vector ( 47 downto 0 )
gt0_track_data_i	std_logic
gt0_block_sync_i	std_logic
gt0_error_count_i	std_logic_vector ( 7 downto 0 )
gt0_frame_check_reset_i	std_logic
gt0_inc_in_i	std_logic
gt0_inc_out_i	std_logic
gt0_unscrambled_data_i	std_logic_vector ( 15 downto 0 )
reset_on_data_error_i	std_logic
track_data_out_i	std_logic
tx_data_vio_control_i	std_logic_vector ( 35 downto 0 )
rx_data_vio_control_i	std_logic_vector ( 35 downto 0 )
shared_vio_control_i	std_logic_vector ( 35 downto 0 )
ila_control_i	std_logic_vector ( 35 downto 0 )
channel_drp_vio_control_i	std_logic_vector ( 35 downto 0 )
common_drp_vio_control_i	std_logic_vector ( 35 downto 0 )
tx_data_vio_async_in_i	std_logic_vector ( 31 downto 0 )
tx_data_vio_sync_in_i	std_logic_vector ( 31 downto 0 )
tx_data_vio_async_out_i	std_logic_vector ( 31 downto 0 )
tx_data_vio_sync_out_i	std_logic_vector ( 31 downto 0 )
rx_data_vio_async_in_i	std_logic_vector ( 31 downto 0 )
rx_data_vio_sync_in_i	std_logic_vector ( 31 downto 0 )
rx_data_vio_async_out_i	std_logic_vector ( 31 downto 0 )
rx_data_vio_sync_out_i	std_logic_vector ( 31 downto 0 )
shared_vio_in_i	std_logic_vector ( 31 downto 0 )
shared_vio_out_i	std_logic_vector ( 31 downto 0 )
ila_in_i	std_logic_vector ( 163 downto 0 )
channel_drp_vio_async_in_i	std_logic_vector ( 31 downto 0 )
channel_drp_vio_sync_in_i	std_logic_vector ( 31 downto 0 )
channel_drp_vio_async_out_i	std_logic_vector ( 31 downto 0 )
channel_drp_vio_sync_out_i	std_logic_vector ( 31 downto 0 )
common_drp_vio_async_in_i	std_logic_vector ( 31 downto 0 )
common_drp_vio_sync_in_i	std_logic_vector ( 31 downto 0 )
common_drp_vio_async_out_i	std_logic_vector ( 31 downto 0 )
common_drp_vio_sync_out_i	std_logic_vector ( 31 downto 0 )
gt0_tx_data_vio_async_in_i	std_logic_vector ( 31 downto 0 )
gt0_tx_data_vio_sync_in_i	std_logic_vector ( 31 downto 0 )
gt0_tx_data_vio_async_out_i	std_logic_vector ( 31 downto 0 )
gt0_tx_data_vio_sync_out_i	std_logic_vector ( 31 downto 0 )
gt0_rx_data_vio_async_in_i	std_logic_vector ( 31 downto 0 )
gt0_rx_data_vio_sync_in_i	std_logic_vector ( 31 downto 0 )
gt0_rx_data_vio_async_out_i	std_logic_vector ( 31 downto 0 )
gt0_rx_data_vio_sync_out_i	std_logic_vector ( 31 downto 0 )
gt0_ila_in_i	std_logic_vector ( 163 downto 0 )
gt0_channel_drp_vio_async_in_i	std_logic_vector ( 31 downto 0 )
gt0_channel_drp_vio_sync_in_i	std_logic_vector ( 31 downto 0 )
gt0_channel_drp_vio_async_out_i	std_logic_vector ( 31 downto 0 )
gt0_channel_drp_vio_sync_out_i	std_logic_vector ( 31 downto 0 )
gt0_common_drp_vio_async_in_i	std_logic_vector ( 31 downto 0 )
gt0_common_drp_vio_sync_in_i	std_logic_vector ( 31 downto 0 )
gt0_common_drp_vio_async_out_i	std_logic_vector ( 31 downto 0 )
gt0_common_drp_vio_sync_out_i	std_logic_vector ( 31 downto 0 )
gttxreset_i	std_logic
gtrxreset_i	std_logic
user_tx_reset_i	std_logic
user_rx_reset_i	std_logic
tx_vio_clk_i	std_logic
tx_vio_clk_mux_out_i	std_logic
rx_vio_ila_clk_i	std_logic
rx_vio_ila_clk_mux_out_i	std_logic
cpllreset_i	std_logic

Attributes
CORE_GENERATION_INFO	string
CORE_GENERATION_INFO	RTL : architecture is " gtwizard_v2_5_gbe_gth , gtwizard_v2_5 , {protocol_file = gigabit_ethernet_CC} "
syn_black_box	boolean
syn_noprune	boolean
syn_black_box	data_vio : component is TRUE
syn_noprune	data_vio : component is TRUE
syn_black_box	icon : component is TRUE
syn_noprune	icon : component is TRUE
keep	string
keep	gt0_txusrclk_i : signal is " true "
keep	gt0_txusrclk2_i : signal is " true "
keep	gt0_rxusrclk_i : signal is " true "
keep	gt0_rxusrclk2_i : signal is " true "

Instantiations
gt0_usrclk_source	gtwizard_v2_5_gbe_gth_GT_USRCLK_SOURCE <Entity gtwizard_v2_5_gbe_gth_GT_USRCLK_SOURCE>
gtwizard_v2_5_gbe_gth_init_i	gtwizard_v2_5_gbe_gth_init <Entity gtwizard_v2_5_gbe_gth_init>
gt0_frame_gen	gtwizard_v2_5_gbe_gth_GT_FRAME_GEN <Entity gtwizard_v2_5_gbe_gth_GT_FRAME_GEN>
gt0_frame_check	gtwizard_v2_5_gbe_gth_GT_FRAME_CHECK <Entity gtwizard_v2_5_gbe_gth_GT_FRAME_CHECK>
icon_i	icon
channel_drp_i	data_vio
common_drp_i	data_vio
shared_vio_i	data_vio
tx_data_vio_i	data_vio
rx_data_vio_i	data_vio
ila_i	ila
gt0_usrclk_source	gtwizard_v2_5_gbe_gth_GT_USRCLK_SOURCE <Entity gtwizard_v2_5_gbe_gth_GT_USRCLK_SOURCE>
gtwizard_v2_5_gbe_gth_init_i	gtwizard_v2_5_gbe_gth_init <Entity gtwizard_v2_5_gbe_gth_init>
gt0_frame_gen	gtwizard_v2_5_gbe_gth_GT_FRAME_GEN <Entity gtwizard_v2_5_gbe_gth_GT_FRAME_GEN>
gt0_frame_check	gtwizard_v2_5_gbe_gth_GT_FRAME_CHECK <Entity gtwizard_v2_5_gbe_gth_GT_FRAME_CHECK>
icon_i	icon
channel_drp_i	data_vio
common_drp_i	data_vio
shared_vio_i	data_vio
tx_data_vio_i	data_vio
rx_data_vio_i	data_vio
ila_i	ila

Member Function Documentation

and_reduce() [1/2]

std_logic and_reduce (   arg in std_logic_vector   )

Function

and_reduce() [2/2]

std_logic and_reduce (   arg in std_logic_vector   )

Function

PROCESS_177()

PROCESS_177	(		gt0_rxusrclk_i,
			gt0_rxresetdone_i
	)

PROCESS_178()

PROCESS_178 (   gt0_txusrclk_i ,   gt0_txfsmresetdone_i   )

Process

PROCESS_738()

PROCESS_738	(		gt0_rxusrclk_i,
			gt0_rxresetdone_i
	)

PROCESS_739()

PROCESS_739 (   gt0_txusrclk_i ,   gt0_txfsmresetdone_i   )

Process

Member Data Documentation

channel_drp_i [1/2]

channel_drp_i data_vio

Instantiation

channel_drp_i [2/2]

channel_drp_i data_vio

Instantiation

channel_drp_vio_async_in_i

channel_drp_vio_async_in_i std_logic_vector ( 31 downto 0 )

Signal

channel_drp_vio_async_out_i

channel_drp_vio_async_out_i std_logic_vector ( 31 downto 0 )

Signal

channel_drp_vio_control_i

channel_drp_vio_control_i std_logic_vector ( 35 downto 0 )

Signal

channel_drp_vio_sync_in_i

channel_drp_vio_sync_in_i std_logic_vector ( 31 downto 0 )

Signal

channel_drp_vio_sync_out_i

channel_drp_vio_sync_out_i std_logic_vector ( 31 downto 0 )

Signal

common_drp_i [1/2]

common_drp_i data_vio

Instantiation

common_drp_i [2/2]

common_drp_i data_vio

Instantiation

common_drp_vio_async_in_i

common_drp_vio_async_in_i std_logic_vector ( 31 downto 0 )

Signal

common_drp_vio_async_out_i

common_drp_vio_async_out_i std_logic_vector ( 31 downto 0 )

Signal

common_drp_vio_control_i

common_drp_vio_control_i std_logic_vector ( 35 downto 0 )

Signal

common_drp_vio_sync_in_i

common_drp_vio_sync_in_i std_logic_vector ( 31 downto 0 )

Signal

common_drp_vio_sync_out_i

common_drp_vio_sync_out_i std_logic_vector ( 31 downto 0 )

Signal

CORE_GENERATION_INFO [1/2]

CORE_GENERATION_INFO string

Attribute

CORE_GENERATION_INFO [2/2]

CORE_GENERATION_INFO RTL : architecture is " gtwizard_v2_5_gbe_gth , gtwizard_v2_5 , {protocol_file = gigabit_ethernet_CC} "

Attribute

cpllreset_i

cpllreset_i std_logic

Signal

CPLLRESET_IN

CPLLRESET_IN std_logic

Signal

data_vio

data_vio

Component

DLY

DLY time := 1 ns

Constant

drpclk_in_i

drpclk_in_i std_logic

Signal

gt0_block_sync_i

gt0_block_sync_i std_logic

Signal

gt0_channel_drp_vio_async_in_i

gt0_channel_drp_vio_async_in_i std_logic_vector ( 31 downto 0 )

Signal

gt0_channel_drp_vio_async_out_i

gt0_channel_drp_vio_async_out_i std_logic_vector ( 31 downto 0 )

Signal

gt0_channel_drp_vio_sync_in_i

gt0_channel_drp_vio_sync_in_i std_logic_vector ( 31 downto 0 )

Signal

gt0_channel_drp_vio_sync_out_i

gt0_channel_drp_vio_sync_out_i std_logic_vector ( 31 downto 0 )

Signal

gt0_common_drp_vio_async_in_i

gt0_common_drp_vio_async_in_i std_logic_vector ( 31 downto 0 )

Signal

gt0_common_drp_vio_async_out_i

gt0_common_drp_vio_async_out_i std_logic_vector ( 31 downto 0 )

Signal

gt0_common_drp_vio_sync_in_i

gt0_common_drp_vio_sync_in_i std_logic_vector ( 31 downto 0 )

Signal

gt0_common_drp_vio_sync_out_i

gt0_common_drp_vio_sync_out_i std_logic_vector ( 31 downto 0 )

Signal

gt0_cpllfbclklost_i

gt0_cpllfbclklost_i std_logic

Signal

gt0_cplllock_i

gt0_cplllock_i std_logic

Signal

gt0_cpllrefclklost_i

gt0_cpllrefclklost_i std_logic

Signal

gt0_cpllreset_i

gt0_cpllreset_i std_logic

Signal

gt0_drpaddr_i

gt0_drpaddr_i std_logic_vector ( 8 downto 0 )

Signal

gt0_drpdi_i

gt0_drpdi_i std_logic_vector ( 15 downto 0 )

Signal

gt0_drpdo_i

gt0_drpdo_i std_logic_vector ( 15 downto 0 )

Signal

gt0_drpen_i

gt0_drpen_i std_logic

Signal

gt0_drprdy_i

gt0_drprdy_i std_logic

Signal

gt0_drpwe_i

gt0_drpwe_i std_logic

Signal

gt0_error_count_i

gt0_error_count_i std_logic_vector ( 7 downto 0 )

Signal

gt0_eyescandataerror_i

gt0_eyescandataerror_i std_logic

Signal

gt0_frame_check [1/2]

gt0_frame_check gtwizard_v2_5_gbe_gth_GT_FRAME_CHECK

Instantiation

gt0_frame_check [2/2]

gt0_frame_check gtwizard_v2_5_gbe_gth_GT_FRAME_CHECK

Instantiation

gt0_frame_check_reset_i

gt0_frame_check_reset_i std_logic

Signal

gt0_frame_gen [1/2]

gt0_frame_gen gtwizard_v2_5_gbe_gth_GT_FRAME_GEN

Instantiation

gt0_frame_gen [2/2]

gt0_frame_gen gtwizard_v2_5_gbe_gth_GT_FRAME_GEN

Instantiation

gt0_gthrxn_i

gt0_gthrxn_i std_logic

Signal

gt0_gthrxp_i

gt0_gthrxp_i std_logic

Signal

gt0_gthtxn_i

gt0_gthtxn_i std_logic

Signal

gt0_gthtxp_i

gt0_gthtxp_i std_logic

Signal

gt0_gtrxreset_i

gt0_gtrxreset_i std_logic

Signal

gt0_gttxreset_i

gt0_gttxreset_i std_logic

Signal

gt0_ila_in_i

gt0_ila_in_i std_logic_vector ( 163 downto 0 )

Signal

gt0_inc_in_i

gt0_inc_in_i std_logic

Signal

gt0_inc_out_i

gt0_inc_out_i std_logic

Signal

gt0_loopback_i

gt0_loopback_i std_logic_vector ( 2 downto 0 )

Signal

gt0_matchn_i

gt0_matchn_i std_logic

Signal

gt0_qplllock_i

gt0_qplllock_i std_logic

Signal

gt0_qpllrefclklost_i

gt0_qpllrefclklost_i std_logic

Signal

gt0_qpllreset_i

gt0_qpllreset_i std_logic

Signal

gt0_rx_data_vio_async_in_i

gt0_rx_data_vio_async_in_i std_logic_vector ( 31 downto 0 )

Signal

gt0_rx_data_vio_async_out_i

gt0_rx_data_vio_async_out_i std_logic_vector ( 31 downto 0 )

Signal

gt0_rx_data_vio_sync_in_i

gt0_rx_data_vio_sync_in_i std_logic_vector ( 31 downto 0 )

Signal

gt0_rx_data_vio_sync_out_i

gt0_rx_data_vio_sync_out_i std_logic_vector ( 31 downto 0 )

Signal

gt0_rx_system_reset_c

gt0_rx_system_reset_c std_logic

Signal

gt0_rxbufreset_i

gt0_rxbufreset_i std_logic

Signal

gt0_rxbufstatus_i

gt0_rxbufstatus_i std_logic_vector ( 2 downto 0 )

Signal

gt0_rxcdrlock_i

gt0_rxcdrlock_i std_logic

Signal

gt0_rxchariscomma_i

gt0_rxchariscomma_i std_logic_vector ( 1 downto 0 )

Signal

gt0_rxcharisk_i

gt0_rxcharisk_i std_logic_vector ( 1 downto 0 )

Signal

gt0_rxclkcorcnt_i

gt0_rxclkcorcnt_i std_logic_vector ( 1 downto 0 )

Signal

gt0_rxdata_i

gt0_rxdata_i std_logic_vector ( 15 downto 0 )

Signal

gt0_rxdisperr_i

gt0_rxdisperr_i std_logic_vector ( 1 downto 0 )

Signal

gt0_rxfsmresetdone_i

gt0_rxfsmresetdone_i std_logic

Signal

gt0_rxmcommaalignen_i

gt0_rxmcommaalignen_i std_logic

Signal

gt0_rxnotintable_i

gt0_rxnotintable_i std_logic_vector ( 1 downto 0 )

Signal

gt0_rxoutclk_i

gt0_rxoutclk_i std_logic

Signal

gt0_rxpcommaalignen_i

gt0_rxpcommaalignen_i std_logic

Signal

gt0_rxpcsreset_i

gt0_rxpcsreset_i std_logic

Signal

gt0_rxpd_i

gt0_rxpd_i std_logic_vector ( 1 downto 0 )

Signal

gt0_rxresetdone_i

gt0_rxresetdone_i std_logic

Signal

gt0_rxresetdone_r

gt0_rxresetdone_r std_logic

Signal

gt0_rxresetdone_r2

gt0_rxresetdone_r2 std_logic

Signal

gt0_rxresetdone_r3

gt0_rxresetdone_r3 std_logic

Signal

gt0_rxuserrdy_i

gt0_rxuserrdy_i std_logic

Signal

gt0_rxusrclk2_i

gt0_rxusrclk2_i std_logic

Signal

gt0_rxusrclk_i

gt0_rxusrclk_i std_logic

Signal

gt0_track_data_i

gt0_track_data_i std_logic

Signal

gt0_tx_data_vio_async_in_i

gt0_tx_data_vio_async_in_i std_logic_vector ( 31 downto 0 )

Signal

gt0_tx_data_vio_async_out_i

gt0_tx_data_vio_async_out_i std_logic_vector ( 31 downto 0 )

Signal

gt0_tx_data_vio_sync_in_i

gt0_tx_data_vio_sync_in_i std_logic_vector ( 31 downto 0 )

Signal

gt0_tx_data_vio_sync_out_i

gt0_tx_data_vio_sync_out_i std_logic_vector ( 31 downto 0 )

Signal

gt0_tx_system_reset_c

gt0_tx_system_reset_c std_logic

Signal

gt0_txbufstatus_i

gt0_txbufstatus_i std_logic_vector ( 1 downto 0 )

Signal

gt0_txchardispmode_i

gt0_txchardispmode_i std_logic_vector ( 1 downto 0 )

Signal

gt0_txchardispval_i

gt0_txchardispval_i std_logic_vector ( 1 downto 0 )

Signal

gt0_txcharisk_float_i

gt0_txcharisk_float_i std_logic_vector ( 5 downto 0 )

Signal

gt0_txcharisk_i

gt0_txcharisk_i std_logic_vector ( 1 downto 0 )

Signal

gt0_txdata_float16_i

gt0_txdata_float16_i std_logic_vector ( 15 downto 0 )

Signal

gt0_txdata_float_i

gt0_txdata_float_i std_logic_vector ( 47 downto 0 )

Signal

gt0_txdata_i

gt0_txdata_i std_logic_vector ( 15 downto 0 )

Signal

gt0_txelecidle_i

gt0_txelecidle_i std_logic

Signal

gt0_txfsmresetdone_i

gt0_txfsmresetdone_i std_logic

Signal

gt0_txfsmresetdone_r

gt0_txfsmresetdone_r std_logic

Signal

gt0_txfsmresetdone_r2

gt0_txfsmresetdone_r2 std_logic

Signal

gt0_txoutclk_i

gt0_txoutclk_i std_logic

Signal

gt0_txoutclkfabric_i

gt0_txoutclkfabric_i std_logic

Signal

gt0_txoutclkpcs_i

gt0_txoutclkpcs_i std_logic

Signal

gt0_txpcsreset_i

gt0_txpcsreset_i std_logic

Signal

gt0_txpd_i

gt0_txpd_i std_logic_vector ( 1 downto 0 )

Signal

gt0_txresetdone_i

gt0_txresetdone_i std_logic

Signal

gt0_txuserrdy_i

gt0_txuserrdy_i std_logic

Signal

gt0_txusrclk2_i

gt0_txusrclk2_i std_logic

Signal

gt0_txusrclk_i

gt0_txusrclk_i std_logic

Signal

gt0_unscrambled_data_i

gt0_unscrambled_data_i std_logic_vector ( 15 downto 0 )

Signal

gt0_usrclk_source [1/2]

gt0_usrclk_source gtwizard_v2_5_gbe_gth_GT_USRCLK_SOURCE

Instantiation

gt0_usrclk_source [2/2]

gt0_usrclk_source gtwizard_v2_5_gbe_gth_GT_USRCLK_SOURCE

Instantiation

gtrxreset_i

gtrxreset_i std_logic

Signal

GTRXRESET_IN

GTRXRESET_IN std_logic

Signal

gttxreset_i

gttxreset_i std_logic

Signal

GTTXRESET_IN

GTTXRESET_IN std_logic

Signal

gtwizard_v2_5_gbe_gth_GT_FRAME_CHECK

gtwizard_v2_5_gbe_gth_GT_FRAME_CHECK

Component

gtwizard_v2_5_gbe_gth_GT_FRAME_GEN

gtwizard_v2_5_gbe_gth_GT_FRAME_GEN

Component

gtwizard_v2_5_gbe_gth_GT_USRCLK_SOURCE

gtwizard_v2_5_gbe_gth_GT_USRCLK_SOURCE

Component

gtwizard_v2_5_gbe_gth_init

gtwizard_v2_5_gbe_gth_init

Component

gtwizard_v2_5_gbe_gth_init_i [1/2]

gtwizard_v2_5_gbe_gth_init_i gtwizard_v2_5_gbe_gth_init

Instantiation

gtwizard_v2_5_gbe_gth_init_i [2/2]

gtwizard_v2_5_gbe_gth_init_i gtwizard_v2_5_gbe_gth_init

Instantiation

icon

icon

Component

icon_i [1/2]

icon_i icon

Instantiation

icon_i [2/2]

icon_i icon

Instantiation

ila

ila

Component

ila_control_i

ila_control_i std_logic_vector ( 35 downto 0 )

Signal

ila_i [1/2]

ila_i ila

Instantiation

ila_i [2/2]

ila_i ila

Instantiation

ila_in_i

ila_in_i std_logic_vector ( 163 downto 0 )

Signal

keep [1/5]

keep string

Attribute

keep [2/5]

keep gt0_txusrclk_i : signal is " true "

Attribute

keep [3/5]

keep gt0_txusrclk2_i : signal is " true "

Attribute

keep [4/5]

keep gt0_rxusrclk_i : signal is " true "

Attribute

keep [5/5]

keep gt0_rxusrclk2_i : signal is " true "

Attribute

q9_clk0_refclk_i

q9_clk0_refclk_i std_logic

Signal

QPLLRESET_IN

QPLLRESET_IN std_logic

Signal

reset_on_data_error_i

reset_on_data_error_i std_logic

Signal

rx_data_vio_async_in_i

rx_data_vio_async_in_i std_logic_vector ( 31 downto 0 )

Signal

rx_data_vio_async_out_i

rx_data_vio_async_out_i std_logic_vector ( 31 downto 0 )

Signal

rx_data_vio_control_i

rx_data_vio_control_i std_logic_vector ( 35 downto 0 )

Signal

rx_data_vio_i [1/2]

rx_data_vio_i data_vio

Instantiation

rx_data_vio_i [2/2]

rx_data_vio_i data_vio

Instantiation

rx_data_vio_sync_in_i

rx_data_vio_sync_in_i std_logic_vector ( 31 downto 0 )

Signal

rx_data_vio_sync_out_i

rx_data_vio_sync_out_i std_logic_vector ( 31 downto 0 )

Signal

rx_vio_ila_clk_i

rx_vio_ila_clk_i std_logic

Signal

rx_vio_ila_clk_mux_out_i

rx_vio_ila_clk_mux_out_i std_logic

Signal

shared_vio_control_i

shared_vio_control_i std_logic_vector ( 35 downto 0 )

Signal

shared_vio_i [1/2]

shared_vio_i data_vio

Instantiation

shared_vio_i [2/2]

shared_vio_i data_vio

Instantiation

shared_vio_in_i

shared_vio_in_i std_logic_vector ( 31 downto 0 )

Signal

shared_vio_out_i

shared_vio_out_i std_logic_vector ( 31 downto 0 )

Signal

syn_black_box [1/3]

syn_black_box boolean

Attribute

syn_black_box [2/3]

syn_black_box data_vio : component is TRUE

Attribute

syn_black_box [3/3]

syn_black_box icon : component is TRUE

Attribute

syn_noprune [1/3]

syn_noprune boolean

Attribute

syn_noprune [2/3]

syn_noprune data_vio : component is TRUE

Attribute

syn_noprune [3/3]

syn_noprune icon : component is TRUE

Attribute

tied_to_ground_i

tied_to_ground_i std_logic

Signal

tied_to_ground_vec_i

tied_to_ground_vec_i std_logic_vector ( 63 downto 0 )

Signal

tied_to_vcc_i

tied_to_vcc_i std_logic

Signal

tied_to_vcc_vec_i

tied_to_vcc_vec_i std_logic_vector ( 7 downto 0 )

Signal

track_data_out_i

track_data_out_i std_logic

Signal

tx_data_vio_async_in_i

tx_data_vio_async_in_i std_logic_vector ( 31 downto 0 )

Signal

tx_data_vio_async_out_i

tx_data_vio_async_out_i std_logic_vector ( 31 downto 0 )

Signal

tx_data_vio_control_i

tx_data_vio_control_i std_logic_vector ( 35 downto 0 )

Signal

tx_data_vio_i [1/2]

tx_data_vio_i data_vio

Instantiation

tx_data_vio_i [2/2]

tx_data_vio_i data_vio

Instantiation

tx_data_vio_sync_in_i

tx_data_vio_sync_in_i std_logic_vector ( 31 downto 0 )

Signal

tx_data_vio_sync_out_i

tx_data_vio_sync_out_i std_logic_vector ( 31 downto 0 )

Signal

tx_vio_clk_i

tx_vio_clk_i std_logic

Signal

tx_vio_clk_mux_out_i

tx_vio_clk_mux_out_i std_logic

Signal

user_rx_reset_i

user_rx_reset_i std_logic

Signal

user_tx_reset_i

user_tx_reset_i std_logic

Signal

---

The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/gtwizard_v2_5_gbe_gth/gtwizard_v2_5_gbe_gth/example_design/gtwizard_v2_5_gbe_gth_exdes.vhd