i2c_master_byte_ctrl Entity Reference

Inheritance diagram for i2c_master_byte_ctrl:

Entities
arch	architecture

Libraries
ieee

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned

Ports
clk	in std_logic
rst	in std_logic
nReset	in std_logic
clk_cnt	in std_logic_vector ( 15 downto 0 )
start	in std_logic
stop	in std_logic
read	in std_logic
write	in std_logic
ack_in	in std_logic
din	in std_logic_vector ( 7 downto 0 )
cmd_ack	out std_logic
ack_out	out std_logic
dout	out std_logic_vector ( 7 downto 0 )
i2c_al	in std_logic
core_cmd	out std_logic_vector ( 3 downto 0 )
core_txd	out std_logic
core_rxd	in std_logic
core_ack	in std_logic

Member Data Documentation

ack_in

ack_in in std_logic

Port

ack_out

ack_out out std_logic

Port

clk

clk in std_logic

Port

clk_cnt

clk_cnt in std_logic_vector ( 15 downto 0 )

Port

cmd_ack

cmd_ack out std_logic

Port

core_ack

core_ack in std_logic

Port

core_cmd

core_cmd out std_logic_vector ( 3 downto 0 )

Port

core_rxd

core_rxd in std_logic

Port

core_txd

core_txd out std_logic

Port

din

din in std_logic_vector ( 7 downto 0 )

Port

dout

dout out std_logic_vector ( 7 downto 0 )

Port

i2c_al

i2c_al in std_logic

Port

ieee

ieee

Library

nReset

nReset in std_logic

Port

read

read in std_logic

Port

rst

rst in std_logic

Port

start

start in std_logic

Port

std_logic_1164

std_logic_1164

Package

std_logic_arith

std_logic_arith

Package

std_logic_unsigned

std_logic_unsigned

Package

stop

stop in std_logic

Port

write

write in std_logic

Port

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The documentation for this class was generated from the following file:

• components/opencores_i2c/firmware/hdl/i2c_master_byte_ctrl.vhd