My Project  v0.0.16
Generics | Ports | Libraries | Use Clauses
i2c_master_top Entity Reference
Inheritance diagram for i2c_master_top:
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Collaboration diagram for i2c_master_top:
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Entities

arch  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 

Generics

ARST_LVL  integer := 0

Ports

wb_clk_i   in std_logic
wb_rst_i   in std_logic
arst_i   in std_logic
wb_adr_i   in std_logic_vector ( 2 downto 0 )
wb_dat_i   in std_logic_vector ( 7 downto 0 )
wb_dat_o   out std_logic_vector ( 7 downto 0 )
wb_we_i   in std_logic
wb_stb_i   in std_logic
wb_cyc_i   in std_logic
wb_ack_o   out std_logic
wb_inta_o   out std_logic
scl_pad_i   in std_logic
scl_pad_o   out std_logic
scl_padoen_o   out std_logic
sda_pad_i   in std_logic
sda_pad_o   out std_logic
sda_padoen_o   out std_logic

Member Data Documentation

◆ arst_i

arst_i in std_logic
Port

◆ ARST_LVL

ARST_LVL integer := 0
Generic

◆ ieee

ieee
Library

◆ scl_pad_i

scl_pad_i in std_logic
Port

◆ scl_pad_o

scl_pad_o out std_logic
Port

◆ scl_padoen_o

scl_padoen_o out std_logic
Port

◆ sda_pad_i

sda_pad_i in std_logic
Port

◆ sda_pad_o

sda_pad_o out std_logic
Port

◆ sda_padoen_o

sda_padoen_o out std_logic
Port

◆ std_logic_1164

std_logic_1164
Package

◆ std_logic_arith

std_logic_arith
Package

◆ std_logic_unsigned

◆ wb_ack_o

wb_ack_o out std_logic
Port

◆ wb_adr_i

wb_adr_i in std_logic_vector ( 2 downto 0 )
Port

◆ wb_clk_i

wb_clk_i in std_logic
Port

◆ wb_cyc_i

wb_cyc_i in std_logic
Port

◆ wb_dat_i

wb_dat_i in std_logic_vector ( 7 downto 0 )
Port

◆ wb_dat_o

wb_dat_o out std_logic_vector ( 7 downto 0 )
Port

◆ wb_inta_o

wb_inta_o out std_logic
Port

◆ wb_rst_i

wb_rst_i in std_logic
Port

◆ wb_stb_i

wb_stb_i in std_logic
Port

◆ wb_we_i

wb_we_i in std_logic
Port

The documentation for this class was generated from the following file: