|
My Project
v0.0.16
|


Entities | |
| arch | architecture |
Libraries | |
| ieee | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_arith | |
| std_logic_unsigned | |
Generics | |
| ARST_LVL | integer := 0 |
Ports | |
| wb_clk_i | in std_logic |
| wb_rst_i | in std_logic |
| arst_i | in std_logic |
| wb_adr_i | in std_logic_vector ( 2 downto 0 ) |
| wb_dat_i | in std_logic_vector ( 7 downto 0 ) |
| wb_dat_o | out std_logic_vector ( 7 downto 0 ) |
| wb_we_i | in std_logic |
| wb_stb_i | in std_logic |
| wb_cyc_i | in std_logic |
| wb_ack_o | out std_logic |
| wb_inta_o | out std_logic |
| scl_pad_i | in std_logic |
| scl_pad_o | out std_logic |
| scl_padoen_o | out std_logic |
| sda_pad_i | in std_logic |
| sda_pad_o | out std_logic |
| sda_padoen_o | out std_logic |
|
Port |
|
Generic |
|
Library |
|
Port |
|
Port |
|
Port |
|
Port |
|
Port |
|
Port |
|
Package |
|
Package |
|
Package |
|
Port |
|
Port |
|
Port |
|
Port |
|
Port |
|
Port |
|
Port |
|
Port |
|
Port |
|
Port |
1.8.13