arch Architecture Reference

Processes
PROCESS_383	( wb_clk_i )
PROCESS_384	( wb_clk_i )
PROCESS_385	( wb_clk_i , rst_i )
PROCESS_945	( wb_clk_i )
PROCESS_946	( wb_clk_i )
PROCESS_947	( wb_clk_i , rst_i )

Components
i2c_master_bit_ctrl	<Entity i2c_master_bit_ctrl>
i2c_master_byte_ctrl	<Entity i2c_master_byte_ctrl>
i2c_master_registers	<Entity i2c_master_registers>

Signals
prer	std_logic_vector ( 15 downto 0 )
ctr	std_logic_vector ( 7 downto 0 )
txr	std_logic_vector ( 7 downto 0 )
rxr	std_logic_vector ( 7 downto 0 )
cr	std_logic_vector ( 7 downto 0 )
sr	std_logic_vector ( 7 downto 0 )
done	std_logic
core_en	std_logic
ien	std_logic
irxack	std_logic
irq_flag	std_logic
i2c_busy	std_logic
i2c_al	std_logic
core_cmd	std_logic_vector ( 3 downto 0 )
core_txd	std_logic
core_ack	std_logic
core_rxd	std_logic
rst_i	std_logic
sta	std_logic
sto	std_logic
rd	std_logic
wr	std_logic
ack	std_logic
iack	std_logic
wb_ack_o_int	std_logic
wb_wacc	std_logic
acki	std_logic

Instantiations
byte_controller	i2c_master_byte_ctrl <Entity i2c_master_byte_ctrl>
bit_controller	i2c_master_bit_ctrl <Entity i2c_master_bit_ctrl>
registers	i2c_master_registers <Entity i2c_master_registers>
byte_controller	i2c_master_byte_ctrl <Entity i2c_master_byte_ctrl>
bit_controller	i2c_master_bit_ctrl <Entity i2c_master_bit_ctrl>
registers	i2c_master_registers <Entity i2c_master_registers>

Member Function Documentation

PROCESS_383()

PROCESS_383 (   wb_clk_i   )

Process

PROCESS_384()

PROCESS_384 (   wb_clk_i   )

Process

PROCESS_385()

PROCESS_385 (   wb_clk_i ,   rst_i   )

Process

PROCESS_945()

PROCESS_945 (   wb_clk_i   )

Process

PROCESS_946()

PROCESS_946 (   wb_clk_i   )

Process

PROCESS_947()

PROCESS_947 (   wb_clk_i ,   rst_i   )

Process

Member Data Documentation

ack

ack std_logic

Signal

acki

acki std_logic

Signal

bit_controller [1/2]

bit_controller i2c_master_bit_ctrl

Instantiation

bit_controller [2/2]

bit_controller i2c_master_bit_ctrl

Instantiation

byte_controller [1/2]

byte_controller i2c_master_byte_ctrl

Instantiation

byte_controller [2/2]

byte_controller i2c_master_byte_ctrl

Instantiation

core_ack

core_ack std_logic

Signal

core_cmd

core_cmd std_logic_vector ( 3 downto 0 )

Signal

core_en

core_en std_logic

Signal

core_rxd

core_rxd std_logic

Signal

core_txd

core_txd std_logic

Signal

cr

cr std_logic_vector ( 7 downto 0 )

Signal

ctr

ctr std_logic_vector ( 7 downto 0 )

Signal

done

done std_logic

Signal

i2c_al

i2c_al std_logic

Signal

i2c_busy

i2c_busy std_logic

Signal

i2c_master_bit_ctrl

i2c_master_bit_ctrl

Component

i2c_master_byte_ctrl

i2c_master_byte_ctrl

Component

i2c_master_registers

i2c_master_registers

Component

iack

iack std_logic

Signal

ien

ien std_logic

Signal

irq_flag

irq_flag std_logic

Signal

irxack

irxack std_logic

Signal

prer

prer std_logic_vector ( 15 downto 0 )

Signal

rd

rd std_logic

Signal

registers [1/2]

registers i2c_master_registers

Instantiation

registers [2/2]

registers i2c_master_registers

Instantiation

rst_i

rst_i std_logic

Signal

rxr

rxr std_logic_vector ( 7 downto 0 )

Signal

sr

sr std_logic_vector ( 7 downto 0 )

Signal

sta

sta std_logic

Signal

sto

sto std_logic

Signal

txr

txr std_logic_vector ( 7 downto 0 )

Signal

wb_ack_o_int

wb_ack_o_int std_logic

Signal

wb_wacc

wb_wacc std_logic

Signal

wr

wr std_logic

Signal

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The documentation for this class was generated from the following file:

• components/opencores_i2c/firmware/hdl/i2c_master_top.vhd