struct Architecture Reference

Processes
PROCESS_392	( clock , l1a_ctrl )

Constants
DELAYofZERO	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ADDR_WIDTH	natural := 9

Signals
countdown	integer := 0
index	integer := 0
busy	std_logic := ' 0 '
load	std_logic := ' 0 '
inc_index	std_logic := ' 0 '
anticlock	std_logic := ' 0 '
delay	std_logic_vector ( 31 downto 0 )
index_addr	std_logic_vector ( ADDR_WIDTH - 2 downto 0 )
num_L1A	std_logic_vector ( ADDR_WIDTH - 2 downto 0 )
ipbw	ipb_wbus_array ( 1 downto 0 )
ipbr	ipb_rbus_array ( 1 downto 0 )
l1a_ctrl	ipb_reg_v ( 1 downto 0 )
l1a_stat	ipb_reg_v ( 0 downto 0 )
run_L1A	std_logic := ' 0 '
runnow	std_logic := ' 0 '
repeat	std_logic := ' 0 '
nowait	std_logic := ' 0 '

Instantiations
block_decode	ipbus_fabric_branch <Entity ipbus_fabric_branch>
control_reg	ipbus_ctrlreg_v <Entity ipbus_ctrlreg_v>
delay_memory	ipbus_dpram <Entity ipbus_dpram>
l1a_gen	L1A_Gen <Entity L1A_Gen>

Member Function Documentation

PROCESS_392()

PROCESS_392	(		clock,
			l1a_ctrl
	)

Member Data Documentation

ADDR_WIDTH

ADDR_WIDTH natural := 9

Constant

anticlock

anticlock std_logic := ' 0 '

Signal

block_decode

block_decode ipbus_fabric_branch

Instantiation

busy

busy std_logic := ' 0 '

Signal

control_reg

control_reg ipbus_ctrlreg_v

Instantiation

countdown

countdown integer := 0

Signal

delay

delay std_logic_vector ( 31 downto 0 )

Signal

delay_memory

delay_memory ipbus_dpram

Instantiation

DELAYofZERO

DELAYofZERO std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Constant

inc_index

inc_index std_logic := ' 0 '

Signal

index

index integer := 0

Signal

index_addr

index_addr std_logic_vector ( ADDR_WIDTH - 2 downto 0 )

Signal

ipbr

ipbr ipb_rbus_array ( 1 downto 0 )

Signal

ipbw

ipbw ipb_wbus_array ( 1 downto 0 )

Signal

l1a_ctrl

l1a_ctrl ipb_reg_v ( 1 downto 0 )

Signal

l1a_gen

l1a_gen L1A_Gen

Instantiation

l1a_stat

l1a_stat ipb_reg_v ( 0 downto 0 )

Signal

load

load std_logic := ' 0 '

Signal

nowait

nowait std_logic := ' 0 '

Signal

num_L1A

num_L1A std_logic_vector ( ADDR_WIDTH - 2 downto 0 )

Signal

repeat

repeat std_logic := ' 0 '

Signal

run_L1A

run_L1A std_logic := ' 0 '

Signal

runnow

runnow std_logic := ' 0 '

Signal

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The documentation for this class was generated from the following file:

• FTM/Control/hdl/ipbus_L1A_Generator.vhd