My Project  v0.0.16
Generics | Ports | Libraries | Use Clauses
ipbus_data_check Entity Reference
Inheritance diagram for ipbus_data_check:
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Collaboration diagram for ipbus_data_check:
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Entities

rtl  architecture
 

Libraries

IEEE 

Use Clauses

STD_LOGIC_1164 
numeric_std 
ipbus  Package <ipbus>

Generics

DPRAM_ADDR_WIDTH  natural
FRAME_SIZE  natural

Ports

ipbus_clk   in std_logic
data_clk   in std_logic
reset   in std_logic
ipbus_in   in ipb_wbus
ipbus_out   out ipb_rbus
ttc_clk   in std_logic
sync   in std_logic
run_in   in std_logic
capture_in   in std_logic
mismatch   out std_logic
data_in   in std_logic_vector ( 31 downto 0 )
ctrl_in   in std_logic_vector ( 3 downto 0 )

Member Data Documentation

◆ capture_in

capture_in in std_logic
Port

◆ ctrl_in

ctrl_in in std_logic_vector ( 3 downto 0 )
Port

◆ data_clk

data_clk in std_logic
Port

◆ data_in

data_in in std_logic_vector ( 31 downto 0 )
Port

◆ DPRAM_ADDR_WIDTH

DPRAM_ADDR_WIDTH natural
Generic

◆ FRAME_SIZE

FRAME_SIZE natural
Generic

◆ IEEE

IEEE
Library

◆ ipbus

ipbus
Package

◆ ipbus_clk

ipbus_clk in std_logic
Port

◆ ipbus_in

ipbus_in in ipb_wbus
Port

◆ ipbus_out

ipbus_out out ipb_rbus
Port

◆ mismatch

mismatch out std_logic
Port

◆ numeric_std

numeric_std
Package

◆ reset

reset in std_logic
Port

◆ run_in

run_in in std_logic
Port

◆ STD_LOGIC_1164

STD_LOGIC_1164
Package

◆ sync

sync in std_logic
Port

◆ ttc_clk

ttc_clk in std_logic
Port

The documentation for this class was generated from the following file: