rtl Architecture Reference

Processes
synchro	( data_clk , run_in )
delaydata	( data_clk , data_in )
reg_mismatch	( data_clk , not_equal )

Signals
pointer_addr	std_logic_vector ( DPRAM_ADDR_WIDTH - 1 downto 0 )
ram_index	unsigned ( DPRAM_ADDR_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
eof	std_logic
run	std_logic
wen	std_logic
rx_data	std_logic_vector ( 31 downto 0 )
ram_data	std_logic_vector ( 31 downto 0 )
null_data	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
not_equal	std_logic

Attributes
keep	string
keep	run : signal is " true "
keep	mismatch : signal is " true "

Instantiations
frame_sync	rx_framing_sync_logic <Entity rx_framing_sync_logic>
ram_pointer	rx_ram_pointer <Entity rx_ram_pointer>
dssram	ipbus_dpram_tob_init <Entity ipbus_dpram_tob_init>

Member Function Documentation

delaydata()

delaydata (   data_clk ,   data_in   )

Process

reg_mismatch()

reg_mismatch	(		data_clk,
			not_equal
	)

synchro()

synchro (   data_clk ,   run_in   )

Process

Member Data Documentation

dssram

dssram ipbus_dpram_tob_init

Instantiation

eof

eof std_logic

Signal

frame_sync

frame_sync rx_framing_sync_logic

Instantiation

keep [1/3]

keep string

Attribute

keep [2/3]

keep run : signal is " true "

Attribute

keep [3/3]

keep mismatch : signal is " true "

Attribute

not_equal

not_equal std_logic

Signal

null_data

null_data std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

pointer_addr

pointer_addr std_logic_vector ( DPRAM_ADDR_WIDTH - 1 downto 0 )

Signal

ram_data

ram_data std_logic_vector ( 31 downto 0 )

Signal

ram_index

ram_index unsigned ( DPRAM_ADDR_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

ram_pointer

ram_pointer rx_ram_pointer

Instantiation

run

run std_logic

Signal

rx_data

rx_data std_logic_vector ( 31 downto 0 )

Signal

wen

wen std_logic

Signal

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The documentation for this class was generated from the following file:

• common/DSS_buffer/hdl/ipbus_data_check.vhd