My Project  v0.0.16
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rx_ram_pointer Entity Reference
Inheritance diagram for rx_ram_pointer:
Inheritance graph
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Entities

rtl  architecture
 

Libraries

IEEE 

Use Clauses

STD_LOGIC_1164 
numeric_std 

Generics

DPRAM_ADDR_WIDTH  natural

Ports

data_clk   in STD_LOGIC
run   in std_logic
eof   in std_logic
capture_in   in std_logic
wen   out std_logic
ram_index   out unsigned ( DPRAM_ADDR_WIDTH - 1 downto 0 )

Member Data Documentation

◆ capture_in

capture_in in std_logic
Port

◆ data_clk

data_clk in STD_LOGIC
Port

◆ DPRAM_ADDR_WIDTH

DPRAM_ADDR_WIDTH natural
Generic

◆ eof

eof in std_logic
Port

◆ IEEE

IEEE
Library

◆ numeric_std

numeric_std
Package

◆ ram_index

ram_index out unsigned ( DPRAM_ADDR_WIDTH - 1 downto 0 )
Port

◆ run

run in std_logic
Port

◆ STD_LOGIC_1164

STD_LOGIC_1164
Package

◆ wen

wen out std_logic
Port

The documentation for this class was generated from the following file: