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My Project
v0.0.16
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Entities | |
| rtl | architecture |
Libraries | |
| IEEE | |
Use Clauses | |
| STD_LOGIC_1164 | |
| numeric_std | |
Generics | |
| DPRAM_ADDR_WIDTH | natural |
Ports | |
| data_clk | in STD_LOGIC |
| run | in std_logic |
| eof | in std_logic |
| capture_in | in std_logic |
| wen | out std_logic |
| ram_index | out unsigned ( DPRAM_ADDR_WIDTH - 1 downto 0 ) |
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1.8.13