rtl Architecture Reference

Processes
synch_run	( data_clk , run )
sync_to_frame	( data_clk , capture_in , begin_ram )
write_gate	( data_clk , index , begin_ram , gate )
synch_address	( data_clk , index , begin_ram )

Constants
MAXRAM	unsigned ( DPRAM_ADDR_WIDTH - 1 downto 0 ) := ( others = > ' 1 ' )

Types
command_state	( idle , wren , done )

Signals
index	unsigned ( DPRAM_ADDR_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
run_b	std_logic := ' 0 '
begin_ram	std_logic := ' 0 '
sequencer	command_state := idle
wen_i	std_logic := ' 0 '
gate	std_logic := ' 0 '
capture	std_logic := ' 0 '

Member Function Documentation

sync_to_frame()

sync_to_frame (   data_clk ,   capture_in ,   begin_ram   )

Process

synch_address()

synch_address (   data_clk ,   index ,   begin_ram   )

Process

synch_run()

synch_run (   data_clk ,   run   )

Process

write_gate()

write_gate (   data_clk ,   index ,   begin_ram ,   gate   )

Process

Member Data Documentation

begin_ram

begin_ram std_logic := ' 0 '

Signal

capture

capture std_logic := ' 0 '

Signal

command_state

command_state ( idle , wren , done )

Type

gate

gate std_logic := ' 0 '

Signal

index

index unsigned ( DPRAM_ADDR_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

MAXRAM

MAXRAM unsigned ( DPRAM_ADDR_WIDTH - 1 downto 0 ) := ( others = > ' 1 ' )

Constant

run_b

run_b std_logic := ' 0 '

Signal

sequencer

sequencer command_state := idle

Signal

wen_i

wen_i std_logic := ' 0 '

Signal

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The documentation for this class was generated from the following file:

• common/DSS_buffer/hdl/rx_ram_pointer.vhd