behave Architecture Reference

Processes
cpu	( )

Constants
N_OOB	natural := 1
BASE_ADD_CTRL_REG	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
BASE_ADD_REG	std_logic_vector ( 31 downto 0 ) := x " 00000002 "
BASE_ADD_RAM	std_logic_vector ( 31 downto 0 ) := x " 00001000 "

Signals
clk	std_logic := ' 1 '
rst	std_logic := ' 1 '
ipb_out_m	ipb_wbus
ipbus_shim_out	ipb_wbus
ipb_in_m	ipb_rbus
ipbus_shim_in	ipb_rbus
oob_in	ipbus_trans_in := ( ' 0 ' , X " 00000000 " , ' 0 ' )
oob_out	ipbus_trans_out := ( X " 000 " , ' 0 ' , ' 0 ' , X " 000 " , X " 00000000 " )
ipbw	ipb_wbus_array ( N_SLAVES - 1 downto 0 )
ipbr	ipb_rbus_array ( N_SLAVES - 1 downto 0 ) := ( others = > IPB_RBUS_NULL )
ctrl_v	ipb_reg_v ( 0 downto 0 )
stat_v	ipb_reg_v ( 0 downto 0 )

Instantiations
ipbus	ipbus_ctrl <Entity ipbus_ctrl>
shim	ipbus_shim <Entity ipbus_shim>
fabric	ipbus_fabric_sel <Entity ipbus_fabric_sel>
ctrl_reg	ipbus_ctrlreg_v <Entity ipbus_ctrlreg_v>
reg	ipbus_reg_v <Entity ipbus_reg_v>
ram	ipbus_ram <Entity ipbus_ram>

Member Function Documentation

cpu()

cpu ( )

Process

Member Data Documentation

BASE_ADD_CTRL_REG

BASE_ADD_CTRL_REG std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Constant

BASE_ADD_RAM

BASE_ADD_RAM std_logic_vector ( 31 downto 0 ) := x " 00001000 "

Constant

BASE_ADD_REG

BASE_ADD_REG std_logic_vector ( 31 downto 0 ) := x " 00000002 "

Constant

clk

clk std_logic := ' 1 '

Signal

ctrl_reg

ctrl_reg ipbus_ctrlreg_v

Instantiation

ctrl_v

ctrl_v ipb_reg_v ( 0 downto 0 )

Signal

fabric

fabric ipbus_fabric_sel

Instantiation

ipb_in_m

ipb_in_m ipb_rbus

Signal

ipb_out_m

ipb_out_m ipb_wbus

Signal

ipbr

ipbr ipb_rbus_array ( N_SLAVES - 1 downto 0 ) := ( others = > IPB_RBUS_NULL )

Signal

ipbus

ipbus ipbus_ctrl

Instantiation

ipbus_shim_in

ipbus_shim_in ipb_rbus

Signal

ipbus_shim_out

ipbus_shim_out ipb_wbus

Signal

ipbw

ipbw ipb_wbus_array ( N_SLAVES - 1 downto 0 )

Signal

N_OOB

N_OOB natural := 1

Constant

oob_in

oob_in ipbus_trans_in := ( ' 0 ' , X " 00000000 " , ' 0 ' )

Signal

oob_out

oob_out ipbus_trans_out := ( X " 000 " , ' 0 ' , ' 0 ' , X " 000 " , X " 00000000 " )

Signal

ram

ram ipbus_ram

Instantiation

reg

reg ipbus_reg_v

Instantiation

rst

rst std_logic := ' 1 '

Signal

shim

shim ipbus_shim

Instantiation

stat_v

stat_v ipb_reg_v ( 0 downto 0 )

Signal

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The documentation for this class was generated from the following file:

• ipbus_lib/boards/ipbus_sim/hdl/ipbus_tb.vhd