rtl Architecture Reference

Constants
ADDR_WIDTH	integer := 8

Signals
pointer_addr	std_logic_vector ( ADDR_WIDTH - 1 downto 0 )
word_counter	unsigned ( ADDR_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
null_data	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
raw_data	std_logic_vector ( 191 downto 0 ) := ( others = > ' 0 ' )
web	std_logic

Instantiations
ttc_tick	ram_slave_pointer
dssram	ipbus_wide_dpram <Entity ipbus_wide_dpram>

Member Data Documentation

ADDR_WIDTH

ADDR_WIDTH integer := 8

Constant

dssram

dssram ipbus_wide_dpram

Instantiation

null_data

null_data std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Signal

pointer_addr

pointer_addr std_logic_vector ( ADDR_WIDTH - 1 downto 0 )

Signal

raw_data

raw_data std_logic_vector ( 191 downto 0 ) := ( others = > ' 0 ' )

Signal

ttc_tick

ttc_tick ram_slave_pointer

Instantiation

web

web std_logic

Signal

word_counter

word_counter unsigned ( ADDR_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

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The documentation for this class was generated from the following file:

• FTM/DSS_Algo/hdl/ipbus_wide_data_source.vhd