My Project
v0.0.16
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Entities | |
rtl | architecture |
Libraries | |
IEEE |
Use Clauses | |
std_logic_1164 | |
std_logic_arith | |
std_logic_unsigned | |
ipbus | Package <ipbus> |
Ports | |
ipbus_clk | in std_logic |
reset | in std_logic |
ipb_in | in ipb_wbus |
ipb_out | out ipb_rbus |
clk | in std_logic |
add_pointer | in std_logic_vector ( 7 downto 0 ) |
tt_data | out std_logic_vector ( 64 * 3 - 1 downto 0 ) |
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