rtl Architecture Reference

Processes
PROCESS_484	( ipbus_clk )

Signals
ack	std_logic
enA	std_logic
weA	std_logic
addrA	std_logic_vector ( 11 downto 0 )
dia	std_logic_vector ( 15 downto 0 )
doa	std_logic_vector ( 15 downto 0 )

Instantiations
asymmetric_ram_tt	asymmetric_ram_tt <Entity asymmetric_ram_tt>

Member Function Documentation

PROCESS_484()

PROCESS_484

(

ipbus_clk

)

Member Data Documentation

ack

ack std_logic

Signal

addrA

addrA std_logic_vector ( 11 downto 0 )

Signal

asymmetric_ram_tt

asymmetric_ram_tt asymmetric_ram_tt

Instantiation

dia

dia std_logic_vector ( 15 downto 0 )

Signal

doa

doa std_logic_vector ( 15 downto 0 )

Signal

enA

enA std_logic

Signal

weA

weA std_logic

Signal

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The documentation for this class was generated from the following file:

• FTM/DSS_Algo/hdl/ipbus_wide_dpram.vhd