My Project  v0.0.16
Signals | Constants | Processes | Instantiations
rtl Architecture Reference

Processes

input_register  ( clock , rx_data_in , clear_error )
data_value  ( clock , comma_detected , next_value )
index_frame  ( clock , comma_detected , word_index )
delay_input  ( clock , rx_in )
count_error  ( clock , error_found , fake_error , clear_counter )

Constants

DELAY  time := 0 . 5 ns
comma_mask  std_logic_vector ( 31 downto 0 ) := x " 007FFF00 "

Signals

rx_in  mgt_data
next_value  unsigned ( 31 downto 0 ) := ( others = > ' 0 ' )
rx_data  unsigned ( 31 downto 0 ) := ( others = > ' 0 ' )
error_counter  unsigned ( ERROR_BITS - 1 downto 0 ) := ( others = > ' 0 ' )
comma_detected  boolean := FALSE
clear_counter  std_logic := ' 0 '
error_found  std_logic := ' 0 '
fake_error  std_logic := ' 0 '
word_index  unsigned ( 2 downto 0 ) := ( others = > ' 0 ' )
masked_data  std_logic_vector ( 31 downto 0 )
crc_start  std_logic := ' 0 '
check_crc  boolean := FALSE
calculated_crc  std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
incoming_crc  std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )

Instantiations

crc32  osum_crc9d32 <Entity osum_crc9d32>

Member Function Documentation

◆ count_error()

count_error (   clock,
  error_found,
  fake_error,
  clear_counter 
)

◆ data_value()

data_value (   clock ,
  comma_detected ,
  next_value  
)
Process

◆ delay_input()

delay_input (   clock ,
  rx_in  
)
Process

◆ index_frame()

index_frame (   clock ,
  comma_detected ,
  word_index  
)
Process

◆ input_register()

input_register (   clock ,
  rx_data_in ,
  clear_error  
)
Process

Member Data Documentation

◆ calculated_crc

calculated_crc std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
Signal

◆ check_crc

check_crc boolean := FALSE
Signal

◆ clear_counter

clear_counter std_logic := ' 0 '
Signal

◆ comma_detected

comma_detected boolean := FALSE
Signal

◆ comma_mask

comma_mask std_logic_vector ( 31 downto 0 ) := x " 007FFF00 "
Constant

◆ crc32

crc32 osum_crc9d32
Instantiation

◆ crc_start

crc_start std_logic := ' 0 '
Signal

◆ DELAY

DELAY time := 0 . 5 ns
Constant

◆ error_counter

error_counter unsigned ( ERROR_BITS - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

◆ error_found

error_found std_logic := ' 0 '
Signal

◆ fake_error

fake_error std_logic := ' 0 '
Signal

◆ incoming_crc

incoming_crc std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
Signal

◆ masked_data

masked_data std_logic_vector ( 31 downto 0 )
Signal

◆ next_value

next_value unsigned ( 31 downto 0 ) := ( others = > ' 0 ' )
Signal

◆ rx_data

rx_data unsigned ( 31 downto 0 ) := ( others = > ' 0 ' )
Signal

◆ rx_in

rx_in mgt_data
Signal

◆ word_index

word_index unsigned ( 2 downto 0 ) := ( others = > ' 0 ' )
Signal

The documentation for this class was generated from the following file: