My Project
v0.0.16
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Entities | |
behavioral | architecture |
Libraries | |
ieee |
Use Clauses | |
std_logic_1164 | |
numeric_std |
Generics | |
REVERSE_BIT_ORDER | boolean := false |
Ports | |
clock | in std_logic |
d_in | in std_logic_vector ( 22 downto 0 ) |
crc_in | in std_logic_vector ( 8 downto 0 ) |
crc_out | out std_logic_vector ( 8 downto 0 ) |
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Port |
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Port |
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Port |
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Library |
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Package |
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Generic |
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Package |