My Project
v0.0.16
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Processes | |
PROCESS_15 | ( clock ) |
Signals | |
d_in_s | std_logic_vector ( 22 downto 0 ) := ( others = > ' 0 ' ) |
crc_in_s | std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' ) |
crc_r | std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' ) |
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Process |
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Signal |
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Signal |
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Signal |