Inheritance diagram for pll_160MHz:
Entities | |
| xilinx | architecture |
Libraries | |
| ieee | |
| unisim | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_unsigned | |
| std_logic_arith | |
| numeric_std | |
| vcomponents | |
Ports | |
| CLK_IN1 | in std_logic |
| CLK_OUT1 | out std_logic |
| RESET | in std_logic |
| LOCKED | out std_logic |
Member Data Documentation
◆ CLK_IN1
|
Port |
◆ CLK_OUT1
|
Port |
◆ ieee
|
Library |
◆ LOCKED
|
Port |
◆ numeric_std
|
Package |
◆ RESET
|
Port |
◆ std_logic_1164
|
Package |
◆ std_logic_arith
|
Package |
◆ std_logic_unsigned
|
Package |
◆ unisim
|
Library |
◆ vcomponents
|
Package |
The documentation for this class was generated from the following file:
- common/TTC_FMC/hdl/decoder_release_1.1/pll_160MHz.vhd
