xilinx Architecture Reference

Signals
clkin1	std_logic
clkfbout	std_logic
clkfbout_buf	std_logic
clkfboutb_unused	std_logic
clkout0	std_logic
clkout0b_unused	std_logic
clkout1_unused	std_logic
clkout1b_unused	std_logic
clkout2_unused	std_logic
clkout2b_unused	std_logic
clkout3_unused	std_logic
clkout3b_unused	std_logic
clkout4_unused	std_logic
clkout5_unused	std_logic
clkout6_unused	std_logic
do_unused	std_logic_vector ( 15 downto 0 )
drdy_unused	std_logic
psdone_unused	std_logic
clkfbstopped_unused	std_logic
clkinstopped_unused	std_logic

Attributes
CORE_GENERATION_INFO	string
CORE_GENERATION_INFO	xilinx : architecture is " dcm_replacement , clk_wiz_v3_6 , {component_name = dcm_replacement , use_phase_alignment = true , use_min_o_jitter = false , use_max_i_jitter = false , use_dyn_phase_shift = false , use_inclk_switchover = false , use_dyn_reconfig = false , feedback_source = FDBK_AUTO , primtype_sel = MMCM_ADV , num_out_clk = 1 , clkin1_period = 6.250 , clkin2_period = 10.000 , use_power_down = false , use_reset = true , use_locked = true , use_inclk_stopped = false , use_status = false , use_freeze = false , use_clk_valid = false , feedback_type = SINGLE , clock_mgr_type = MANUAL , manual_override = false} "

Instantiations
mmcm_adv_inst	mmcm_adv
clkf_buf	bufg
clkout1_buf	bufg

Member Data Documentation

clkf_buf

clkf_buf bufg

Instantiation

clkfbout

clkfbout std_logic

Signal

clkfbout_buf

clkfbout_buf std_logic

Signal

clkfboutb_unused

clkfboutb_unused std_logic

Signal

clkfbstopped_unused

clkfbstopped_unused std_logic

Signal

clkin1

clkin1 std_logic

Signal

clkinstopped_unused

clkinstopped_unused std_logic

Signal

clkout0

clkout0 std_logic

Signal

clkout0b_unused

clkout0b_unused std_logic

Signal

clkout1_buf

clkout1_buf bufg

Instantiation

clkout1_unused

clkout1_unused std_logic

Signal

clkout1b_unused

clkout1b_unused std_logic

Signal

clkout2_unused

clkout2_unused std_logic

Signal

clkout2b_unused

clkout2b_unused std_logic

Signal

clkout3_unused

clkout3_unused std_logic

Signal

clkout3b_unused

clkout3b_unused std_logic

Signal

clkout4_unused

clkout4_unused std_logic

Signal

clkout5_unused

clkout5_unused std_logic

Signal

clkout6_unused

clkout6_unused std_logic

Signal

CORE_GENERATION_INFO [1/2]

CORE_GENERATION_INFO string

Attribute

CORE_GENERATION_INFO [2/2]

CORE_GENERATION_INFO xilinx : architecture is " dcm_replacement , clk_wiz_v3_6 , {component_name = dcm_replacement , use_phase_alignment = true , use_min_o_jitter = false , use_max_i_jitter = false , use_dyn_phase_shift = false , use_inclk_switchover = false , use_dyn_reconfig = false , feedback_source = FDBK_AUTO , primtype_sel = MMCM_ADV , num_out_clk = 1 , clkin1_period = 6.250 , clkin2_period = 10.000 , use_power_down = false , use_reset = true , use_locked = true , use_inclk_stopped = false , use_status = false , use_freeze = false , use_clk_valid = false , feedback_type = SINGLE , clock_mgr_type = MANUAL , manual_override = false} "

Attribute

do_unused

do_unused std_logic_vector ( 15 downto 0 )

Signal

drdy_unused

drdy_unused std_logic

Signal

mmcm_adv_inst

mmcm_adv_inst mmcm_adv

Instantiation

psdone_unused

psdone_unused std_logic

Signal

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The documentation for this class was generated from the following file:

• common/TTC_FMC/hdl/decoder_release_1.1/pll_160MHz.vhd