imp Architecture Reference

Functions
integer	Get_Addr_Bits ( y: in std_logic_vector( 31 downto 0) )

Processes
REGISTERING_RESET_P	( S_AXI_ACLK )
REGISTERING_RESET_P2	( S_AXI_ACLK )
Access_Control	( S_AXI_ACLK )
S_AXI_RDATA_RESP_P	( S_AXI_ACLK )
S_AXI_RVALID_I_P	( S_AXI_ACLK )
S_AXI_BRESP_P	( S_AXI_ACLK )
S_AXI_BVALID_I_P	( S_AXI_ACLK )
DPTO_CNT_P	( S_AXI_ACLK )

Constants
CS_BUS_SIZE	integer := C_ARD_ADDR_RANGE_ARRAY ' length/ 2
CE_BUS_SIZE	integer := calc_num_ce ( C_ARD_NUM_CE_ARRAY )
C_ADDR_DECODE_BITS	integer := Get_Addr_Bits ( C_S_AXI_MIN_SIZE )
C_NUM_DECODE_BITS	integer := C_ADDR_DECODE_BITS + 1
ZEROS	std_logic_vector ( ( C_IPIF_ABUS_WIDTH - 1 ) downto ( C_ADDR_DECODE_BITS + 1 ) ) := ( others = > ' 0 ' )
COUNTER_WIDTH	integer := clog2 ( ( C_DPHASE_TIMEOUT ) )

Types
BUS_ACCESS_STATES	( SM_IDLE , SM_READ , SM_WRITE , SM_RESP )

Signals
s_axi_bvalid_i	std_logic := ' 0 '
s_axi_arready_i	std_logic
s_axi_rvalid_i	std_logic := ' 0 '
start	std_logic
start2	std_logic
bus2ip_addr_i	std_logic_vector ( ( C_IPIF_ABUS_WIDTH - 1 ) downto 0 )
timeout	std_logic
rd_done	std_logic
wr_done	std_logic
rd_done1	std_logic
wr_done1	std_logic
wrack_1	std_logic
rdack_1	std_logic
rst	std_logic
temp_i	std_logic
state	BUS_ACCESS_STATES
cs_for_gaps_i	std_logic
bus2ip_rnw_i	std_logic
s_axi_bresp_i	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
s_axi_rresp_i	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
s_axi_rdata_i	std_logic_vector ( C_IPIF_DBUS_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
is_read	std_logic
is_write	std_logic
dpto_cnt	std_logic_vector ( COUNTER_WIDTH downto 0 )

Attributes
DowngradeIPIdentifiedWarnings	string
DowngradeIPIdentifiedWarnings	imp : architecture is " yes "

Instantiations
i_decoder	address_decoder <Entity address_decoder>

Member Function Documentation

Access_Control()

Access_Control (   S_AXI_ACLK   )

Process

DPTO_CNT_P()

DPTO_CNT_P (   S_AXI_ACLK   )

Process

Get_Addr_Bits()

integer Get_Addr_Bits (   y in std_logic_vector( 31 downto 0 )   )

Function

REGISTERING_RESET_P()

REGISTERING_RESET_P

(

S_AXI_ACLK

)

REGISTERING_RESET_P2()

REGISTERING_RESET_P2 (   S_AXI_ACLK   )

Process

S_AXI_BRESP_P()

S_AXI_BRESP_P (   S_AXI_ACLK   )

Process

S_AXI_BVALID_I_P()

S_AXI_BVALID_I_P (   S_AXI_ACLK   )

Process

S_AXI_RDATA_RESP_P()

S_AXI_RDATA_RESP_P (   S_AXI_ACLK   )

Process

S_AXI_RVALID_I_P()

S_AXI_RVALID_I_P (   S_AXI_ACLK   )

Process

Member Data Documentation

bus2ip_addr_i

bus2ip_addr_i std_logic_vector ( ( C_IPIF_ABUS_WIDTH - 1 ) downto 0 )

Signal

bus2ip_rnw_i

bus2ip_rnw_i std_logic

Signal

BUS_ACCESS_STATES

BUS_ACCESS_STATES ( SM_IDLE , SM_READ , SM_WRITE , SM_RESP )

Type

C_ADDR_DECODE_BITS

C_ADDR_DECODE_BITS integer := Get_Addr_Bits ( C_S_AXI_MIN_SIZE )

Constant

C_NUM_DECODE_BITS

C_NUM_DECODE_BITS integer := C_ADDR_DECODE_BITS + 1

Constant

CE_BUS_SIZE

CE_BUS_SIZE integer := calc_num_ce ( C_ARD_NUM_CE_ARRAY )

Constant

COUNTER_WIDTH

COUNTER_WIDTH integer := clog2 ( ( C_DPHASE_TIMEOUT ) )

Constant

CS_BUS_SIZE

CS_BUS_SIZE integer := C_ARD_ADDR_RANGE_ARRAY ' length/ 2

Constant

cs_for_gaps_i

cs_for_gaps_i std_logic

Signal

DowngradeIPIdentifiedWarnings [1/2]

DowngradeIPIdentifiedWarnings string

Attribute

DowngradeIPIdentifiedWarnings [2/2]

DowngradeIPIdentifiedWarnings imp : architecture is " yes "

Attribute

dpto_cnt

dpto_cnt std_logic_vector ( COUNTER_WIDTH downto 0 )

Signal

i_decoder

i_decoder address_decoder

Instantiation

is_read

is_read std_logic

Signal

is_write

is_write std_logic

Signal

rd_done

rd_done std_logic

Signal

rd_done1

rd_done1 std_logic

Signal

rdack_1

rdack_1 std_logic

Signal

rst

rst std_logic

Signal

s_axi_arready_i

s_axi_arready_i std_logic

Signal

s_axi_bresp_i

s_axi_bresp_i std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )

Signal

s_axi_bvalid_i

s_axi_bvalid_i std_logic := ' 0 '

Signal

s_axi_rdata_i

s_axi_rdata_i std_logic_vector ( C_IPIF_DBUS_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

s_axi_rresp_i

s_axi_rresp_i std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )

Signal

s_axi_rvalid_i

s_axi_rvalid_i std_logic := ' 0 '

Signal

start

start std_logic

Signal

start2

start2 std_logic

Signal

state

state BUS_ACCESS_STATES

Signal

temp_i

temp_i std_logic

Signal

timeout

timeout std_logic

Signal

wr_done

wr_done std_logic

Signal

wr_done1

wr_done1 std_logic

Signal

wrack_1

wrack_1 std_logic

Signal

ZEROS

ZEROS std_logic_vector ( ( C_IPIF_ABUS_WIDTH - 1 ) downto ( C_ADDR_DECODE_BITS + 1 ) ) := ( others = > ' 0 ' )

Constant

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The documentation for this class was generated from the following file:

• IP/temac_gbe_v9_0_gmii/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd