spi_interface Entity Reference

Entities
behave	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
std_logic_unsigned

Generics
width	integer

Ports
clk	in std_logic
rst	in std_logic
spi_miso	out std_logic
spi_mosi	in std_logic
spi_sck	in std_logic
spi_cs_b	in std_logic
buf_wdata	out std_logic_vector ( width - 1 DOWNTO 0 ) := ( others = > ' 0 ' )
buf_we	out std_logic := ' 0 '
buf_rdata	in std_logic_vector ( width - 1 DOWNTO 0 )
buf_re	out std_logic := ' 0 '
buf_req	out std_logic := ' 0 '
buf_done	in std_logic := ' 0 '

Member Data Documentation

buf_done

buf_done in std_logic := ' 0 '

Port

buf_rdata

buf_rdata in std_logic_vector ( width - 1 DOWNTO 0 )

Port

buf_re

buf_re out std_logic := ' 0 '

Port

buf_req

buf_req out std_logic := ' 0 '

Port

buf_wdata

buf_wdata out std_logic_vector ( width - 1 DOWNTO 0 ) := ( others = > ' 0 ' )

Port

buf_we

buf_we out std_logic := ' 0 '

Port

clk

clk in std_logic

Port

IEEE

IEEE

Library

rst

rst in std_logic

Port

spi_cs_b

spi_cs_b in std_logic

Port

spi_miso

spi_miso out std_logic

Port

spi_mosi

spi_mosi in std_logic

Port

spi_sck

spi_sck in std_logic

Port

STD_LOGIC_1164

STD_LOGIC_1164

Package

std_logic_unsigned

std_logic_unsigned

Package

width

width integer

Generic

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The documentation for this class was generated from the following file:

• components/ipbus_slaves/firmware/hdl/uc_spi_interface.vhd