behave Architecture Reference

Processes
sreg_proc	( clk , rst )
ModeProcess	( clk , rst )
SerialInProcess	( clk , rst )
SerialOutProcess	( clk , rst )
sreg_proc	( clk , rst )
ModeProcess	( clk , rst )
SerialInProcess	( clk , rst )
SerialOutProcess	( clk , rst )

Constants
timeout_max	integer := 1073741823

Types
type_rx_state	( RX_IDLE , RX_ACTIVE )
type_tx_state	( TX_IDLE , TX_ACTIVE )
type_mode	( IDLE_MODE , HEADER_MODE , READ_MODE , WRITE_MODE )

Signals
sck_sreg	std_logic_vector ( 2 downto 0 )
si_sreg	std_logic_vector ( 2 downto 0 )
cs_sreg	std_logic_vector ( 2 downto 0 )
SerialInActive	std_logic
SerialInValid	std_logic
SerialInRegister	std_logic_vector ( width - 1 downto 0 )
SerialInIndex	integer range 0 to width - 1
SerialInTimeout	integer range 0 to 1073741823
SerialOutActive	std_logic
SerialOutValid	std_logic
SerialOutValidDelayed	std_logic
SerialOutValidDelayed2	std_logic
SerialOutRegister	std_logic_vector ( width - 1 downto 0 )
SerialOutIndex	integer range 0 to width - 1
SerialOutTimeout	integer range 0 to 1073741823
r_nw	std_logic
status_reg	std_logic_vector ( width - 1 downto 0 )
sck_rising_edge	std_logic
rx_state	type_rx_state := RX_IDLE
tx_state	type_tx_state := TX_IDLE
mode	type_mode := IDLE_MODE

Attributes
enum_encoding	string
enum_encoding	type_rx_state : type is " 0 1 "
enum_encoding	type_tx_state : type is " 0 1 "
enum_encoding	type_mode : type is " 00 01 10 11 "

Member Function Documentation

ModeProcess() [1/2]

ModeProcess (   clk ,   rst   )

Process

ModeProcess() [2/2]

ModeProcess (   clk ,   rst   )

Process

SerialInProcess() [1/2]

SerialInProcess (   clk ,   rst   )

Process

SerialInProcess() [2/2]

SerialInProcess (   clk ,   rst   )

Process

SerialOutProcess() [1/2]

SerialOutProcess (   clk ,   rst   )

Process

SerialOutProcess() [2/2]

SerialOutProcess (   clk ,   rst   )

Process

sreg_proc() [1/2]

sreg_proc (   clk ,   rst   )

Process

sreg_proc() [2/2]

sreg_proc (   clk ,   rst   )

Process

Member Data Documentation

cs_sreg

cs_sreg std_logic_vector ( 2 downto 0 )

Signal

enum_encoding [1/4]

enum_encoding string

Attribute

enum_encoding [2/4]

enum_encoding type_rx_state : type is " 0 1 "

Attribute

enum_encoding [3/4]

enum_encoding type_tx_state : type is " 0 1 "

Attribute

enum_encoding [4/4]

enum_encoding type_mode : type is " 00 01 10 11 "

Attribute

mode

mode type_mode := IDLE_MODE

Signal

r_nw

r_nw std_logic

Signal

rx_state

rx_state type_rx_state := RX_IDLE

Signal

sck_rising_edge

sck_rising_edge std_logic

Signal

sck_sreg

sck_sreg std_logic_vector ( 2 downto 0 )

Signal

SerialInActive

SerialInActive std_logic

Signal

SerialInIndex

SerialInIndex integer range 0 to width - 1

Signal

SerialInRegister

SerialInRegister std_logic_vector ( width - 1 downto 0 )

Signal

SerialInTimeout

SerialInTimeout integer range 0 to 1073741823

Signal

SerialInValid

SerialInValid std_logic

Signal

SerialOutActive

SerialOutActive std_logic

Signal

SerialOutIndex

SerialOutIndex integer range 0 to width - 1

Signal

SerialOutRegister

SerialOutRegister std_logic_vector ( width - 1 downto 0 )

Signal

SerialOutTimeout

SerialOutTimeout integer range 0 to 1073741823

Signal

SerialOutValid

SerialOutValid std_logic

Signal

SerialOutValidDelayed

SerialOutValidDelayed std_logic

Signal

SerialOutValidDelayed2

SerialOutValidDelayed2 std_logic

Signal

si_sreg

si_sreg std_logic_vector ( 2 downto 0 )

Signal

status_reg

status_reg std_logic_vector ( width - 1 downto 0 )

Signal

timeout_max

timeout_max integer := 1073741823

Constant

tx_state

tx_state type_tx_state := TX_IDLE

Signal

type_mode

type_mode ( IDLE_MODE , HEADER_MODE , READ_MODE , WRITE_MODE )

Type

type_rx_state

type_rx_state ( RX_IDLE , RX_ACTIVE )

Type

type_tx_state

type_tx_state ( TX_IDLE , TX_ACTIVE )

Type

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The documentation for this class was generated from the following file:

• components/ipbus_slaves/firmware/hdl/uc_spi_interface.vhd