rtl Architecture Reference

Processes
PROCESS_40	( clk )

Signals
d_sync	std_logic
d_sync_d	std_logic
d_edge	std_logic
d25	std_logic
d25_d	std_logic
q_i	std_logic

Instantiations
clkdiv	clock_div <Entity clock_div>

Member Function Documentation

PROCESS_40()

PROCESS_40

(

clk

)

Member Data Documentation

clkdiv

clkdiv clock_div

Instantiation

d25

d25 std_logic

Signal

d25_d

d25_d std_logic

Signal

d_edge

d_edge std_logic

Signal

d_sync

d_sync std_logic

Signal

d_sync_d

d_sync_d std_logic

Signal

q_i

q_i std_logic

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_core/firmware/hdl/stretcher.vhd