structural Architecture Reference

Signals
data_sync1	std_logic

Attributes
ASYNC_REG	string
ASYNC_REG	data_sync1 : signal is " TRUE "
RLOC	string
RLOC	data_sync1 : signal is " X0Y0 "
RLOC	data_out : signal is " X0Y0 "

Instantiations
data_sync	fd
data_sync_reg	fd
data_sync	fd
data_sync_reg	fd

Member Data Documentation

ASYNC_REG [1/2]

ASYNC_REG string

Attribute

ASYNC_REG [2/2]

ASYNC_REG data_sync1 : signal is " TRUE "

Attribute

data_sync [1/2]

data_sync fd

Instantiation

data_sync [2/2]

data_sync fd

Instantiation

data_sync1

data_sync1 std_logic

Signal

data_sync_reg [1/2]

data_sync_reg fd

Instantiation

data_sync_reg [2/2]

data_sync_reg fd

Instantiation

RLOC [1/3]

RLOC string

Attribute

RLOC [2/3]

RLOC data_sync1 : signal is " X0Y0 "

Attribute

RLOC [3/3]

RLOC data_out : signal is " X0Y0 "

Attribute

---

The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/v6_emac_v2_3_basex/sync_block.vhd