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My Project
v0.0.16
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Entities | |
| rtl | architecture |
Libraries | |
| IEEE | |
Use Clauses | |
| STD_LOGIC_1164 | |
| numeric_std | |
Generics | |
| COUNT_BITS | positive := 8 |
Ports | |
| fast_clk | in STD_LOGIC |
| base_clock | in std_logic |
| stop | in std_logic |
| clk_count | out std_logic_vector ( COUNT_BITS - 1 downto 0 ) |
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1.8.13