My Project  v0.0.16
Generics | Ports | Libraries | Use Clauses
tdc Entity Reference
Inheritance diagram for tdc:
Inheritance graph
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Entities

rtl  architecture
 

Libraries

IEEE 

Use Clauses

STD_LOGIC_1164 
numeric_std 

Generics

COUNT_BITS  positive := 8

Ports

fast_clk   in STD_LOGIC
base_clock   in std_logic
stop   in std_logic
clk_count   out std_logic_vector ( COUNT_BITS - 1 downto 0 )

Member Data Documentation

◆ base_clock

base_clock in std_logic
Port

◆ clk_count

clk_count out std_logic_vector ( COUNT_BITS - 1 downto 0 )
Port

◆ COUNT_BITS

COUNT_BITS positive := 8
Generic

◆ fast_clk

fast_clk in STD_LOGIC
Port

◆ IEEE

IEEE
Library

◆ numeric_std

numeric_std
Package

◆ STD_LOGIC_1164

STD_LOGIC_1164
Package

◆ stop

stop in std_logic
Port

The documentation for this class was generated from the following file: