rtl Architecture Reference

Processes
clk_to_sig	( base_clock , clock_signal )
grab_count	( fast_clk , grab , stop )
frontend	( fast_clk , head , clock_signal )
ne_frontend	( fast_clk , ne_head , clock_signal )
counter	( fast_clk , pe_trigger , delay_count )
delay_neg	( fast_clk , pe_trigger , ne_trigger )
frame_tick	( fast_clk , stop , delay_count )

Constants
MAXCOUNT	natural := ( 2 ** ( COUNT_BITS - 1 ) ) - 1
DELAY	time := 1 ns

Signals
clock_signal	std_logic := ' 0 '
head	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
ne_head	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
pe_trigger	std_logic := ' 0 '
ne_trigger	std_logic := ' 0 '
delay_count	natural range 0 to MAXCOUNT := 0
neg_pre_pos	std_logic := ' 0 '
grab	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )

Member Function Documentation

clk_to_sig()

clk_to_sig (   base_clock ,   clock_signal   )

Process

counter()

counter (   fast_clk ,   pe_trigger ,   delay_count   )

Process

delay_neg()

delay_neg (   fast_clk ,   pe_trigger ,   ne_trigger   )

Process

frame_tick()

frame_tick (   fast_clk ,   stop ,   delay_count   )

Process

frontend()

frontend (   fast_clk ,   head ,   clock_signal   )

Process

grab_count()

grab_count (   fast_clk ,   grab ,   stop   )

Process

ne_frontend()

ne_frontend (   fast_clk ,   ne_head ,   clock_signal   )

Process

Member Data Documentation

clock_signal

clock_signal std_logic := ' 0 '

Signal

DELAY

DELAY time := 1 ns

Constant

delay_count

delay_count natural range 0 to MAXCOUNT := 0

Signal

grab

grab std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )

Signal

head

head std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )

Signal

MAXCOUNT

MAXCOUNT natural := ( 2 ** ( COUNT_BITS - 1 ) ) - 1

Constant

ne_head

ne_head std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )

Signal

ne_trigger

ne_trigger std_logic := ' 0 '

Signal

neg_pre_pos

neg_pre_pos std_logic := ' 0 '

Signal

pe_trigger

pe_trigger std_logic := ' 0 '

Signal

---

The documentation for this class was generated from the following file:

• common/Misc/hdl/tdc.vhd