behav Architecture Reference

Processes
WaveGen_Proc	( )

Constants
COUNT_BITS	positive := 4
FRAME_SIZE	positive := 7
fast_period	time := 3 . 6 ns
slow_period	time := 25 ns

Signals
fast_clk	STD_LOGIC := ' 0 '
slow_clk	std_logic := ' 0 '
stop	std_logic := ' 0 '
clk_count	std_logic_vector ( COUNT_BITS - 1 downto 0 )

Instantiations
dut	tdc <Entity tdc>

Member Function Documentation

WaveGen_Proc()

WaveGen_Proc

(

)

Member Data Documentation

clk_count

clk_count std_logic_vector ( COUNT_BITS - 1 downto 0 )

Signal

COUNT_BITS

COUNT_BITS positive := 4

Constant

dut

dut tdc

Instantiation

fast_clk

fast_clk STD_LOGIC := ' 0 '

Signal

fast_period

fast_period time := 3 . 6 ns

Constant

FRAME_SIZE

FRAME_SIZE positive := 7

Constant

slow_clk

slow_clk std_logic := ' 0 '

Signal

slow_period

slow_period time := 25 ns

Constant

stop

stop std_logic := ' 0 '

Signal

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The documentation for this class was generated from the following file:

• testbench/tdc_tb.vhd