temac_gbe_v9_0_gmii_block Entity Reference

Inheritance diagram for temac_gbe_v9_0_gmii_block:

Collaboration diagram for temac_gbe_v9_0_gmii_block:

Entities
wrapper	architecture

Libraries
unisim
ieee
tri_mode_ethernet_mac_v9_0_15

Use Clauses
vcomponents
std_logic_1164
all

Ports
gtx_clk	in std_logic
glbl_rstn	in std_logic
rx_axi_rstn	in std_logic
tx_axi_rstn	in std_logic
rx_statistics_vector	out std_logic_vector ( 27 downto 0 )
rx_statistics_valid	out std_logic
rx_mac_aclk	out std_logic
rx_reset	out std_logic
rx_axis_mac_tdata	out std_logic_vector ( 7 downto 0 )
rx_axis_mac_tvalid	out std_logic
rx_axis_mac_tlast	out std_logic
rx_axis_mac_tuser	out std_logic
tx_ifg_delay	in std_logic_vector ( 7 downto 0 )
tx_statistics_vector	out std_logic_vector ( 31 downto 0 )
tx_statistics_valid	out std_logic
tx_mac_aclk	out std_logic
tx_reset	out std_logic
tx_axis_mac_tdata	in std_logic_vector ( 7 downto 0 )
tx_axis_mac_tvalid	in std_logic
tx_axis_mac_tlast	in std_logic
tx_axis_mac_tuser	in std_logic_vector ( 0 downto 0 )
tx_axis_mac_tready	out std_logic
pause_req	in std_logic
pause_val	in std_logic_vector ( 15 downto 0 )
speedis100	out std_logic
speedis10100	out std_logic
gmii_txd	out std_logic_vector ( 7 downto 0 )
gmii_tx_en	out std_logic
gmii_tx_er	out std_logic
gmii_tx_clk	out std_logic
gmii_rxd	in std_logic_vector ( 7 downto 0 )
gmii_rx_dv	in std_logic
gmii_rx_er	in std_logic
gmii_rx_clk	in std_logic
rx_configuration_vector	in std_logic_vector ( 79 downto 0 )
tx_configuration_vector	in std_logic_vector ( 79 downto 0 )

Member Data Documentation

all

all

Package

glbl_rstn

glbl_rstn in std_logic

Port

gmii_rx_clk

gmii_rx_clk in std_logic

Port

gmii_rx_dv

gmii_rx_dv in std_logic

Port

gmii_rx_er

gmii_rx_er in std_logic

Port

gmii_rxd

gmii_rxd in std_logic_vector ( 7 downto 0 )

Port

gmii_tx_clk

gmii_tx_clk out std_logic

Port

gmii_tx_en

gmii_tx_en out std_logic

Port

gmii_tx_er

gmii_tx_er out std_logic

Port

gmii_txd

gmii_txd out std_logic_vector ( 7 downto 0 )

Port

gtx_clk

gtx_clk in std_logic

Port

ieee

ieee

Library

pause_req

pause_req in std_logic

Port

pause_val

pause_val in std_logic_vector ( 15 downto 0 )

Port

rx_axi_rstn

rx_axi_rstn in std_logic

Port

rx_axis_mac_tdata

rx_axis_mac_tdata out std_logic_vector ( 7 downto 0 )

Port

rx_axis_mac_tlast

rx_axis_mac_tlast out std_logic

Port

rx_axis_mac_tuser

rx_axis_mac_tuser out std_logic

Port

rx_axis_mac_tvalid

rx_axis_mac_tvalid out std_logic

Port

rx_configuration_vector

rx_configuration_vector in std_logic_vector ( 79 downto 0 )

Port

rx_mac_aclk

rx_mac_aclk out std_logic

Port

rx_reset

rx_reset out std_logic

Port

rx_statistics_valid

rx_statistics_valid out std_logic

Port

rx_statistics_vector

rx_statistics_vector out std_logic_vector ( 27 downto 0 )

Port

speedis100

speedis100 out std_logic

Port

speedis10100

speedis10100 out std_logic

Port

std_logic_1164

std_logic_1164

Package

tri_mode_ethernet_mac_v9_0_15

tri_mode_ethernet_mac_v9_0_15

Library

tx_axi_rstn

tx_axi_rstn in std_logic

Port

tx_axis_mac_tdata

tx_axis_mac_tdata in std_logic_vector ( 7 downto 0 )

Port

tx_axis_mac_tlast

tx_axis_mac_tlast in std_logic

Port

tx_axis_mac_tready

tx_axis_mac_tready out std_logic

Port

tx_axis_mac_tuser

tx_axis_mac_tuser in std_logic_vector ( 0 downto 0 )

Port

tx_axis_mac_tvalid

tx_axis_mac_tvalid in std_logic

Port

tx_configuration_vector

tx_configuration_vector in std_logic_vector ( 79 downto 0 )

Port

tx_ifg_delay

tx_ifg_delay in std_logic_vector ( 7 downto 0 )

Port

tx_mac_aclk

tx_mac_aclk out std_logic

Port

tx_reset

tx_reset out std_logic

Port

tx_statistics_valid

tx_statistics_valid out std_logic

Port

tx_statistics_vector

tx_statistics_vector out std_logic_vector ( 31 downto 0 )

Port

unisim

unisim

Library

vcomponents

vcomponents

Package

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The documentation for this class was generated from the following file:

• IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_block.vhd