wrapper Architecture Reference

Components
tri_mode_ethernet_mac_v9_0_15
temac_gbe_v9_0_gmii_gmii_if	<Entity temac_gbe_v9_0_gmii_gmii_if>
temac_gbe_v9_0_gmii_block_sync_block

Signals
gmii_tx_en_int	std_logic
gmii_tx_er_int	std_logic
gmii_txd_int	std_logic_vector ( 7 downto 0 )
gmii_rx_dv_int	std_logic
gmii_rx_er_int	std_logic
gmii_rxd_int	std_logic_vector ( 7 downto 0 )
speedis100_int	std_logic
speedis10100_int	std_logic
rx_mac_aclk_int	std_logic
tx_mac_aclk_int	std_logic
tx_reset_int	std_logic
rx_reset_int	std_logic
rx_statistics_vector_int	std_logic_vector ( 31 downto 0 )
rx_statistics_valid_int	std_logic
tx_statistics_vector_int	std_logic_vector ( 39 downto 0 )
tx_statistics_valid_int	std_logic
tx_axis_mac_tuser_int	std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' )

Instantiations
gmii_interface	temac_gbe_v9_0_gmii_gmii_if <Entity temac_gbe_v9_0_gmii_gmii_if>
temac_gbe_v9_0_gmii_core	tri_mode_ethernet_mac_v9_0_15

Member Data Documentation

gmii_interface

gmii_interface temac_gbe_v9_0_gmii_gmii_if

Instantiation

gmii_rx_dv_int

gmii_rx_dv_int std_logic

Signal

gmii_rx_er_int

gmii_rx_er_int std_logic

Signal

gmii_rxd_int

gmii_rxd_int std_logic_vector ( 7 downto 0 )

Signal

gmii_tx_en_int

gmii_tx_en_int std_logic

Signal

gmii_tx_er_int

gmii_tx_er_int std_logic

Signal

gmii_txd_int

gmii_txd_int std_logic_vector ( 7 downto 0 )

Signal

rx_mac_aclk_int

rx_mac_aclk_int std_logic

Signal

rx_reset_int

rx_reset_int std_logic

Signal

rx_statistics_valid_int

rx_statistics_valid_int std_logic

Signal

rx_statistics_vector_int

rx_statistics_vector_int std_logic_vector ( 31 downto 0 )

Signal

speedis100_int

speedis100_int std_logic

Signal

speedis10100_int

speedis10100_int std_logic

Signal

temac_gbe_v9_0_gmii_block_sync_block

temac_gbe_v9_0_gmii_block_sync_block

Component

temac_gbe_v9_0_gmii_core

temac_gbe_v9_0_gmii_core tri_mode_ethernet_mac_v9_0_15

Instantiation

temac_gbe_v9_0_gmii_gmii_if

temac_gbe_v9_0_gmii_gmii_if

Component

tri_mode_ethernet_mac_v9_0_15

tri_mode_ethernet_mac_v9_0_15

Component

tx_axis_mac_tuser_int

tx_axis_mac_tuser_int std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' )

Signal

tx_mac_aclk_int

tx_mac_aclk_int std_logic

Signal

tx_reset_int

tx_reset_int std_logic

Signal

tx_statistics_valid_int

tx_statistics_valid_int std_logic

Signal

tx_statistics_vector_int

tx_statistics_vector_int std_logic_vector ( 39 downto 0 )

Signal

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The documentation for this class was generated from the following file:

• IP/temac_gbe_v9_0_gmii/synth/temac_gbe_v9_0_gmii_block.vhd