top_FTM_DSS Entity Reference

Inheritance diagram for top_FTM_DSS:

Collaboration diagram for top_FTM_DSS:

Entities
rtl	architecture

Libraries
IEEE
unisim
ftm

Use Clauses
STD_LOGIC_1164
VComponents
ipbus	Package <ipbus>
spi	Package <spi>
ftm	Package <ftm>

Generics
FLAVOUR	integer := 0
	Integer used to distinguish different FPGAs having a slightly different firmware.
OFFICIAL	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	bit 31 is official, bit 30:16 reserved, bit 15:0 AWE attempt number
GLOBAL_FWDATE	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Date format DDMMYYYY in decimal.
GLOBAL_FWTIME	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Time format 00HHMMSS in decimal.
GLOBAL_FWHASH	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the repository.
GLOBAL_FWVERSION	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of the repository (format: MMmmcccc in hex)
TOP_FWHASH	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the top folder: list files, tcl file.
TOP_FWVERSION	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of the top folder, see TOP_FWHASH.
XML_HASH	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the XMLs.
XML_VERSION	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of the XMLs.
HOG_FWHASH	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the Hog submodule.
FTM_FWHASH	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git sha.
FTM_FWVERSION	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of algolib library (format: MMmmcccc in hex)
IPBUS_LIB_FWHASH	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the ipbus submodule.

Ports
Q119_REFCLK1_N	in std_logic
Q119_REFCLK1_P	in std_logic
Q118_REFCLK1_N	in std_logic
Q118_REFCLK1_P	in std_logic
Q117_REFCLK1_N	in std_logic
Q117_REFCLK1_P	in std_logic
Q116_REFCLK1_N	in std_logic
Q116_REFCLK1_P	in std_logic
Q115_REFCLK1_N	in std_logic
Q115_REFCLK1_P	in std_logic
Q114_REFCLK1_N	in std_logic
Q114_REFCLK1_P	in std_logic
Q219_REFCLK1_N	in std_logic
Q219_REFCLK1_P	in std_logic
Q218_REFCLK1_N	in std_logic
Q218_REFCLK1_P	in std_logic
Q217_REFCLK1_N	in std_logic
Q217_REFCLK1_P	in std_logic
Q216_REFCLK1_N	in std_logic
Q216_REFCLK1_P	in std_logic
Q215_REFCLK1_N	in std_logic
Q215_REFCLK1_P	in std_logic
Q214_REFCLK1_N	in std_logic
Q214_REFCLK1_P	in std_logic
RXN_IN	in std_logic_vector ( 47 downto 0 )
RXP_IN	in std_logic_vector ( 47 downto 0 )
TXN_OUT	out std_logic_vector ( 47 downto 0 )
TXP_OUT	out std_logic_vector ( 47 downto 0 )
sysclk_p	in STD_LOGIC
sysclk_n	in STD_LOGIC
ttc_clk_p	in STD_LOGIC
ttc_clk_n	in STD_LOGIC
fpga_number	in STD_LOGIC
pcb_version	in std_logic
slave_rx_data_p	in std_logic_vector ( 8 DOWNTO 0 )
slave_rx_data_n	in std_logic_vector ( 8 DOWNTO 0 )
slave_rx_parity_p	in std_logic
slave_rx_parity_n	in std_logic
slave_tx_pause_p	in std_logic
slave_tx_pause_n	in std_logic
slave_tx_data_p	out std_logic_vector ( 8 DOWNTO 0 )
slave_tx_data_n	out std_logic_vector ( 8 DOWNTO 0 )
slave_tx_parity_p	out std_logic
slave_tx_parity_n	out std_logic
dss_reset	in STD_LOGIC
test_pin1	out std_logic
test_pin2	out std_logic
test_pin3	out std_logic
test_pin4	out std_logic
nc_pin1	out std_logic
ttc_sync_p	in std_logic
ttc_sync_n	in std_logic
ttc_run_p	in std_logic
ttc_run_n	in std_logic
config_csn	out STD_LOGIC
config_mosi	out STD_LOGIC
config_miso	in STD_LOGIC

Member Data Documentation

config_csn

config_csn out STD_LOGIC

Port

config_miso

config_miso in STD_LOGIC

Port

config_mosi

config_mosi out STD_LOGIC

Port

dss_reset

dss_reset in STD_LOGIC

Port

FLAVOUR

FLAVOUR integer := 0

Generic

Integer used to distinguish different FPGAs having a slightly different firmware.

fpga_number

fpga_number in STD_LOGIC

Port

ftm [1/2]

ftm

Library

ftm [2/2]

ftm

Package

FTM_FWHASH

FTM_FWHASH std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Short 7-digit git sha.

FTM_FWVERSION

FTM_FWVERSION std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Version of algolib library (format: MMmmcccc in hex)

GLOBAL_FWDATE

GLOBAL_FWDATE std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Date format DDMMYYYY in decimal.

GLOBAL_FWHASH

GLOBAL_FWHASH std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Short 7-digit git SHA of the repository.

GLOBAL_FWTIME

GLOBAL_FWTIME std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Time format 00HHMMSS in decimal.

GLOBAL_FWVERSION

GLOBAL_FWVERSION std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Version of the repository (format: MMmmcccc in hex)

HOG_FWHASH

HOG_FWHASH std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Short 7-digit git SHA of the Hog submodule.

IEEE

IEEE

Library

ipbus

ipbus

Package

IPBUS_LIB_FWHASH

IPBUS_LIB_FWHASH std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Short 7-digit git SHA of the ipbus submodule.

nc_pin1

nc_pin1 out std_logic

Port

OFFICIAL

OFFICIAL std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

bit 31 is official, bit 30:16 reserved, bit 15:0 AWE attempt number

pcb_version

pcb_version in std_logic

Port

Q114_REFCLK1_N

Q114_REFCLK1_N in std_logic

Port

Q114_REFCLK1_P

Q114_REFCLK1_P in std_logic

Port

Q115_REFCLK1_N

Q115_REFCLK1_N in std_logic

Port

Q115_REFCLK1_P

Q115_REFCLK1_P in std_logic

Port

Q116_REFCLK1_N

Q116_REFCLK1_N in std_logic

Port

Q116_REFCLK1_P

Q116_REFCLK1_P in std_logic

Port

Q117_REFCLK1_N

Q117_REFCLK1_N in std_logic

Port

Q117_REFCLK1_P

Q117_REFCLK1_P in std_logic

Port

Q118_REFCLK1_N

Q118_REFCLK1_N in std_logic

Port

Q118_REFCLK1_P

Q118_REFCLK1_P in std_logic

Port

Q119_REFCLK1_N

Q119_REFCLK1_N in std_logic

Port

Q119_REFCLK1_P

Q119_REFCLK1_P in std_logic

Port

Q214_REFCLK1_N

Q214_REFCLK1_N in std_logic

Port

Q214_REFCLK1_P

Q214_REFCLK1_P in std_logic

Port

Q215_REFCLK1_N

Q215_REFCLK1_N in std_logic

Port

Q215_REFCLK1_P

Q215_REFCLK1_P in std_logic

Port

Q216_REFCLK1_N

Q216_REFCLK1_N in std_logic

Port

Q216_REFCLK1_P

Q216_REFCLK1_P in std_logic

Port

Q217_REFCLK1_N

Q217_REFCLK1_N in std_logic

Port

Q217_REFCLK1_P

Q217_REFCLK1_P in std_logic

Port

Q218_REFCLK1_N

Q218_REFCLK1_N in std_logic

Port

Q218_REFCLK1_P

Q218_REFCLK1_P in std_logic

Port

Q219_REFCLK1_N

Q219_REFCLK1_N in std_logic

Port

Q219_REFCLK1_P

Q219_REFCLK1_P in std_logic

Port

RXN_IN

RXN_IN in std_logic_vector ( 47 downto 0 )

Port

RXP_IN

RXP_IN in std_logic_vector ( 47 downto 0 )

Port

slave_rx_data_n

slave_rx_data_n in std_logic_vector ( 8 DOWNTO 0 )

Port

slave_rx_data_p

slave_rx_data_p in std_logic_vector ( 8 DOWNTO 0 )

Port

slave_rx_parity_n

slave_rx_parity_n in std_logic

Port

slave_rx_parity_p

slave_rx_parity_p in std_logic

Port

slave_tx_data_n

slave_tx_data_n out std_logic_vector ( 8 DOWNTO 0 )

Port

slave_tx_data_p

slave_tx_data_p out std_logic_vector ( 8 DOWNTO 0 )

Port

slave_tx_parity_n

slave_tx_parity_n out std_logic

Port

slave_tx_parity_p

slave_tx_parity_p out std_logic

Port

slave_tx_pause_n

slave_tx_pause_n in std_logic

Port

slave_tx_pause_p

slave_tx_pause_p in std_logic

Port

spi

spi

Package

STD_LOGIC_1164

STD_LOGIC_1164

Package

sysclk_n

sysclk_n in STD_LOGIC

Port

sysclk_p

sysclk_p in STD_LOGIC

Port

test_pin1

test_pin1 out std_logic

Port

test_pin2

test_pin2 out std_logic

Port

test_pin3

test_pin3 out std_logic

Port

test_pin4

test_pin4 out std_logic

Port

TOP_FWHASH

TOP_FWHASH std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Short 7-digit git SHA of the top folder: list files, tcl file.

TOP_FWVERSION

TOP_FWVERSION std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Version of the top folder, see TOP_FWHASH.

ttc_clk_n

ttc_clk_n in STD_LOGIC

Port

ttc_clk_p

ttc_clk_p in STD_LOGIC

Port

ttc_run_n

ttc_run_n in std_logic

Port

ttc_run_p

ttc_run_p in std_logic

Port

ttc_sync_n

ttc_sync_n in std_logic

Port

ttc_sync_p

ttc_sync_p in std_logic

Port

TXN_OUT

TXN_OUT out std_logic_vector ( 47 downto 0 )

Port

TXP_OUT

TXP_OUT out std_logic_vector ( 47 downto 0 )

Port

unisim

unisim

Library

VComponents

VComponents

Package

XML_HASH

XML_HASH std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Short 7-digit git SHA of the XMLs.

XML_VERSION

XML_VERSION std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Version of the XMLs.

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The documentation for this class was generated from the following file:

• Top/FTM_DSS/top_FTM_DSS.vhd