rtl Architecture Reference

Processes
PROCESS_955	( mgt_source_clk2 (i ) , mgt_source_data (i ) )
PROCESS_956	( mgt_sink_clk2 (i ) , mgt_sink_data_prereg (i ) )
PROCESS_957	( clk125 , slave_tx_data , slave_tx_parity , slave_rx_data , slave_rx_parity )

Constants
N_TXS	positive := 48
N_RXS	positive := 12

Signals
slave_tx_data	std_logic_vector ( 8 DOWNTO 0 )
slave_tx_data_reg	std_logic_vector ( 8 DOWNTO 0 )
slave_rx_data	std_logic_vector ( 8 DOWNTO 0 )
slave_rx_data_reg	std_logic_vector ( 8 DOWNTO 0 )
slave_rx_err	std_logic
slave_tx_pause	std_logic
slave_tx_parity	std_logic
slave_tx_parity_reg	std_logic
slave_rx_parity	std_logic
slave_rx_parity_reg	std_logic
slave_rx_parity_chk	std_logic_vector ( 9 DOWNTO 0 )
clk125	STD_LOGIC
ipb_clk	STD_LOGIC
rst_125	STD_LOGIC
rst_ipb	STD_LOGIC
clk_40M	STD_LOGIC
mac_tx_data	std_logic_vector ( 7 downto 0 )
mac_rx_data	std_logic_vector ( 7 downto 0 )
mac_tx_valid	std_logic
mac_tx_last	std_logic
mac_tx_error	std_logic
mac_tx_ready	std_logic
mac_rx_valid	std_logic
mac_rx_last	std_logic
mac_rx_error	std_logic
ipb_master_out	ipb_wbus
ipb_master_in	ipb_rbus
mac_addr	std_logic_vector ( 47 downto 0 )
ip_addr	std_logic_vector ( 31 downto 0 )
sys_rst	std_logic
flash_o_int	spi_mo
flash_i_int	spi_mi
dss_sync	std_logic := ' 0 '
dss_run	std_logic := ' 0 '
mgt_clk	std_logic := ' 0 '
gtrefclk	std_logic := ' 0 '
ttc_40Mclk	std_logic
mgt_source_data	mgt_data_array ( N_TXS - 1 downto 0 )
mgt_source_clk2	std_logic_vector ( N_TXS - 1 downto 0 )
mgt_sink_data	mgt_data_array ( N_RXS - 1 downto 0 )
mgt_sink_clk2	std_logic_vector ( N_RXS - 1 downto 0 )
mgt_source_data_regd	mgt_data_array ( N_TXS - 1 downto 0 )
mgt_sink_data_prereg	mgt_data_array ( N_RXS - 1 downto 0 )
IPBus_port_default	std_logic_vector ( 15 downto 0 ) := x " C352 "
IPBus_port_this	std_logic_vector ( 15 downto 0 )
Remote_Got_IP_addr	std_logic
soft_reset_tx	std_logic := ' 0 '
soft_reset_rx	std_logic := ' 0 '
mgt_tx_reset	std_logic := ' 0 '
mgt_rx_reset	std_logic := ' 0 '
mgt_control	mgt_control_array ( 3 downto 0 )
mgt_status	mgt_status_array ( 3 downto 0 )
tx_reset_done	std_logic_vector ( 47 downto 0 )
locked	std_logic := ' 0 '
txmonitor	std_logic := ' 0 '
rxmonitor	std_logic := ' 0 '
tied_to_vcc_i	std_logic := ' 1 '
prototype_pcb	std_logic := ' 1 '

Attributes
mark_debug	string
mark_debug	mgt_sink_data_prereg : signal is " true "

Instantiations
mgts_217_219	DSS_3quads_11g2_mgts <Entity DSS_3quads_11g2_mgts>
mgts_214_216	DSS_3quads_11g2_mgts <Entity DSS_3quads_11g2_mgts>
mgts_117_119	DSS_3quads_11g2_mgts <Entity DSS_3quads_11g2_mgts>
mgts_114_116	DSS_3quads_11g2_mgts <Entity DSS_3quads_11g2_mgts>
detect_txcomma0	comma_monitor <Entity comma_monitor>
detect_rxcomma0	comma_monitor <Entity comma_monitor>
ibuf_40m	ibufgds
bufg_ttc	bufg
clocks	clocks_7s_extphy <Entity clocks_7s_extphy>
s2m	obufds
s2mp	obufds
m2s	ibufds
m2s_err	ibufds
m2s_pause	ibufds
interconnect_slave	UDP_slave_if <Entity UDP_slave_if>
ipbus	ipbus_ctrl <Entity ipbus_ctrl>
ttc_info_spin	ibufds
ttc_info_sync	ibufds
slaves	slaves <Entity slaves>
cclk_o	startup <Entity startup>

Member Function Documentation

PROCESS_955()

PROCESS_955	(		mgt_source_clk2(i ),
			mgt_source_data(i )
	)

PROCESS_956()

PROCESS_956 (   mgt_sink_clk2 (i ) ,   mgt_sink_data_prereg (i )   )

Process

PROCESS_957()

PROCESS_957	(		clk125,
			slave_tx_data,
			slave_tx_parity,
			slave_rx_data,
			slave_rx_parity
	)

Member Data Documentation

bufg_ttc

bufg_ttc bufg

Instantiation

cclk_o

cclk_o startup

Instantiation

clk125

clk125 STD_LOGIC

Signal

clk_40M

clk_40M STD_LOGIC

Signal

clocks

clocks clocks_7s_extphy

Instantiation

detect_rxcomma0

detect_rxcomma0 comma_monitor

Instantiation

detect_txcomma0

detect_txcomma0 comma_monitor

Instantiation

dss_run

dss_run std_logic := ' 0 '

Signal

dss_sync

dss_sync std_logic := ' 0 '

Signal

flash_i_int

flash_i_int spi_mi

Signal

flash_o_int

flash_o_int spi_mo

Signal

gtrefclk

gtrefclk std_logic := ' 0 '

Signal

ibuf_40m

ibuf_40m ibufgds

Instantiation

interconnect_slave

interconnect_slave UDP_slave_if

Instantiation

ip_addr

ip_addr std_logic_vector ( 31 downto 0 )

Signal

ipb_clk

ipb_clk STD_LOGIC

Signal

ipb_master_in

ipb_master_in ipb_rbus

Signal

ipb_master_out

ipb_master_out ipb_wbus

Signal

ipbus

ipbus ipbus_ctrl

Instantiation

IPBus_port_default

IPBus_port_default std_logic_vector ( 15 downto 0 ) := x " C352 "

Signal

IPBus_port_this

IPBus_port_this std_logic_vector ( 15 downto 0 )

Signal

locked

locked std_logic := ' 0 '

Signal

m2s

m2s ibufds

Instantiation

m2s_err

m2s_err ibufds

Instantiation

m2s_pause

m2s_pause ibufds

Instantiation

mac_addr

mac_addr std_logic_vector ( 47 downto 0 )

Signal

mac_rx_data

mac_rx_data std_logic_vector ( 7 downto 0 )

Signal

mac_rx_error

mac_rx_error std_logic

Signal

mac_rx_last

mac_rx_last std_logic

Signal

mac_rx_valid

mac_rx_valid std_logic

Signal

mac_tx_data

mac_tx_data std_logic_vector ( 7 downto 0 )

Signal

mac_tx_error

mac_tx_error std_logic

Signal

mac_tx_last

mac_tx_last std_logic

Signal

mac_tx_ready

mac_tx_ready std_logic

Signal

mac_tx_valid

mac_tx_valid std_logic

Signal

mark_debug [1/2]

mark_debug string

Attribute

mark_debug [2/2]

mark_debug mgt_sink_data_prereg : signal is " true "

Attribute

mgt_clk

mgt_clk std_logic := ' 0 '

Signal

mgt_control

mgt_control mgt_control_array ( 3 downto 0 )

Signal

mgt_rx_reset

mgt_rx_reset std_logic := ' 0 '

Signal

mgt_sink_clk2

mgt_sink_clk2 std_logic_vector ( N_RXS - 1 downto 0 )

Signal

mgt_sink_data

mgt_sink_data mgt_data_array ( N_RXS - 1 downto 0 )

Signal

mgt_sink_data_prereg

mgt_sink_data_prereg mgt_data_array ( N_RXS - 1 downto 0 )

Signal

mgt_source_clk2

mgt_source_clk2 std_logic_vector ( N_TXS - 1 downto 0 )

Signal

mgt_source_data

mgt_source_data mgt_data_array ( N_TXS - 1 downto 0 )

Signal

mgt_source_data_regd

mgt_source_data_regd mgt_data_array ( N_TXS - 1 downto 0 )

Signal

mgt_status

mgt_status mgt_status_array ( 3 downto 0 )

Signal

mgt_tx_reset

mgt_tx_reset std_logic := ' 0 '

Signal

mgts_114_116

mgts_114_116 DSS_3quads_11g2_mgts

Instantiation

mgts_117_119

mgts_117_119 DSS_3quads_11g2_mgts

Instantiation

mgts_214_216

mgts_214_216 DSS_3quads_11g2_mgts

Instantiation

mgts_217_219

mgts_217_219 DSS_3quads_11g2_mgts

Instantiation

N_RXS

N_RXS positive := 12

Constant

N_TXS

N_TXS positive := 48

Constant

prototype_pcb

prototype_pcb std_logic := ' 1 '

Signal

Remote_Got_IP_addr

Remote_Got_IP_addr std_logic

Signal

rst_125

rst_125 STD_LOGIC

Signal

rst_ipb

rst_ipb STD_LOGIC

Signal

rxmonitor

rxmonitor std_logic := ' 0 '

Signal

s2m

s2m obufds

Instantiation

s2mp

s2mp obufds

Instantiation

slave_rx_data

slave_rx_data std_logic_vector ( 8 DOWNTO 0 )

Signal

slave_rx_data_reg

slave_rx_data_reg std_logic_vector ( 8 DOWNTO 0 )

Signal

slave_rx_err

slave_rx_err std_logic

Signal

slave_rx_parity

slave_rx_parity std_logic

Signal

slave_rx_parity_chk

slave_rx_parity_chk std_logic_vector ( 9 DOWNTO 0 )

Signal

slave_rx_parity_reg

slave_rx_parity_reg std_logic

Signal

slave_tx_data

slave_tx_data std_logic_vector ( 8 DOWNTO 0 )

Signal

slave_tx_data_reg

slave_tx_data_reg std_logic_vector ( 8 DOWNTO 0 )

Signal

slave_tx_parity

slave_tx_parity std_logic

Signal

slave_tx_parity_reg

slave_tx_parity_reg std_logic

Signal

slave_tx_pause

slave_tx_pause std_logic

Signal

slaves

slaves slaves

Instantiation

soft_reset_rx

soft_reset_rx std_logic := ' 0 '

Signal

soft_reset_tx

soft_reset_tx std_logic := ' 0 '

Signal

sys_rst

sys_rst std_logic

Signal

tied_to_vcc_i

tied_to_vcc_i std_logic := ' 1 '

Signal

ttc_40Mclk

ttc_40Mclk std_logic

Signal

ttc_info_spin

ttc_info_spin ibufds

Instantiation

ttc_info_sync

ttc_info_sync ibufds

Instantiation

tx_reset_done

tx_reset_done std_logic_vector ( 47 downto 0 )

Signal

txmonitor

txmonitor std_logic := ' 0 '

Signal

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The documentation for this class was generated from the following file:

• Top/FTM_DSS/top_FTM_DSS.vhd