top_ftm_control Entity Reference

Inheritance diagram for top_ftm_control:

Collaboration diagram for top_ftm_control:

Entities
rtl	architecture

Libraries
IEEE
unisim
ftm

Use Clauses
STD_LOGIC_1164
numeric_std
VComponents
ipbus	Package <ipbus>
mac_arbiter_decl	Package <mac_arbiter_decl>
ftm	Package <ftm>
ftm_mgt	Package <ftm_mgt>
spi	Package <spi>

Generics
FLAVOUR	integer := 0
	Integer used to distinguish different FPGAs having a slightly different firmware.
OFFICIAL	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	bit 31 is official, bit 30:16 reserved, bit 15:0 AWE attempt number
GLOBAL_FWDATE	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Date format DDMMYYYY in decimal.
GLOBAL_FWTIME	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Time format 00HHMMSS in decimal.
GLOBAL_FWHASH	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the repository.
GLOBAL_FWVERSION	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of the repository (format: MMmmcccc in hex)
TOP_FWHASH	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the top folder: list files, tcl file.
TOP_FWVERSION	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of the top folder, see TOP_FWHASH.
XML_HASH	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the XMLs.
XML_VERSION	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of the XMLs.
HOG_FWHASH	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the Hog submodule.
FTM_FWHASH	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git sha.
FTM_FWVERSION	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Version of algolib library (format: MMmmcccc in hex)
IPBUS_LIB_FWHASH	std_logic_vector ( 31 downto 0 ) := x " 00000000 "
	Short 7-digit git SHA of the ipbus submodule.
NSRC	positive := 3

Ports
Q118_REFCLK1_N	in std_logic
Q118_REFCLK1_P	in std_logic
Q117_REFCLK1_N	in std_logic
Q117_REFCLK1_P	in std_logic
Q116_REFCLK1_N	in std_logic
Q116_REFCLK1_P	in std_logic
Q115_REFCLK1_N	in std_logic
Q115_REFCLK1_P	in std_logic
RXN_IN_115_116	in std_logic_vector ( 7 downto 0 )
RXP_IN_115_116	in std_logic_vector ( 7 downto 0 )
TXN_OUT_115_116	out std_logic_vector ( 7 downto 0 )
TXP_OUT_115_116	out std_logic_vector ( 7 downto 0 )
RXN_IN_117_118	in std_logic_vector ( 7 downto 0 )
RXP_IN_117_118	in std_logic_vector ( 7 downto 0 )
TXN_OUT_117_118	out std_logic_vector ( 7 downto 0 )
TXP_OUT_117_118	out std_logic_vector ( 7 downto 0 )
sysclk_p	in STD_LOGIC
sysclk_n	in STD_LOGIC
clk40M_p	in STD_LOGIC
clk40M_n	in STD_LOGIC
gmii_gtx_clk	out STD_LOGIC
gmii_tx_en	out STD_LOGIC
gmii_tx_er	out STD_LOGIC
gmii_txd	out STD_LOGIC_VECTOR ( 7 downto 0 )
gmii_rx_clk	in STD_LOGIC
gmii_rx_dv	in STD_LOGIC
gmii_rx_er	in STD_LOGIC
gmii_rxd	in STD_LOGIC_VECTOR ( 7 downto 0 )
phy_rstb	out STD_LOGIC
hw_addr	in std_logic_vector ( 4 downto 0 )
node_led_n	out std_logic
aerr_led_n	out std_logic
alert_led_n	out std_logic
hub1_led_n	out std_logic
force_mac_n	in std_logic
lappio_n	in std_logic_vector ( 3 downto 0 )
pcb_version_n	in std_logic_vector ( 1 downto 0 )
rot_switch	in std_logic_vector ( 3 downto 0 )
master1_tx_data_p	in std_logic_vector ( 8 DOWNTO 0 )
master1_tx_data_n	in std_logic_vector ( 8 DOWNTO 0 )
master1_tx_parity_p	in std_logic
master1_tx_parity_n	in std_logic
master1_rx_data_p	out std_logic_vector ( 8 DOWNTO 0 )
master1_rx_data_n	out std_logic_vector ( 8 DOWNTO 0 )
master1_rx_parity_p	out std_logic
master1_rx_parity_n	out std_logic
master1_tx_pause_p	out std_logic
master1_tx_pause_n	out std_logic
master2_tx_data_p	in std_logic_vector ( 8 DOWNTO 0 )
master2_tx_data_n	in std_logic_vector ( 8 DOWNTO 0 )
master2_tx_parity_p	in std_logic
master2_tx_parity_n	in std_logic
master2_rx_data_p	out std_logic_vector ( 8 DOWNTO 0 )
master2_rx_data_n	out std_logic_vector ( 8 DOWNTO 0 )
master2_rx_parity_p	out std_logic
master2_rx_parity_n	out std_logic
master2_tx_pause_p	out std_logic
master2_tx_pause_n	out std_logic
dss_prog_b	out std_logic_vector ( 2 downto 1 )
dss_done	in std_logic_vector ( 2 downto 1 )
dss_init_b	in std_logic_vector ( 2 downto 1 )
dss_reset	out std_logic_vector ( 2 downto 1 )
pll_mosi	out STD_LOGIC
pll_clk	out STD_LOGIC
pll_miso	in STD_LOGIC
pll_le_b	out std_logic_vector ( 3 downto 0 )
pll_powerdn_b	out STD_LOGIC
pll_sync_b	out std_logic_vector ( 3 downto 0 )
pll_lock	in STD_LOGIC_VECTOR ( 3 downto 0 )
config_csn	out STD_LOGIC
config_mosi	out STD_LOGIC
config_miso	in STD_LOGIC
flash_csn	out STD_LOGIC
flash_mosi	out STD_LOGIC
flash_clk	out STD_LOGIC
flash_miso	in STD_LOGIC
flash_sel_b	out std_logic_vector ( 2 downto 1 )
cdrclk_p	in std_logic
cdrclk_n	in std_logic
cdr40M_p	in std_logic
cdr40M_n	in std_logic
cdrdata_p	in std_logic
cdrdata_n	in std_logic
ttc_los	in std_logic
ttc_lol	in std_logic
div_rstn	out std_logic
div_div4	out std_logic
ttcfmc_2de	out std_logic
not_ttc	in std_logic
run_dss1_p	out std_logic
run_dss1_n	out std_logic
sync_dss1_p	out std_logic
sync_dss1_n	out std_logic
run_dss2_p	out std_logic
run_dss2_n	out std_logic
sync_dss2_p	out std_logic
sync_dss2_n	out std_logic
ttcfmc_led	out std_logic
vadj_off	out std_logic
fmc_lemo1in_p	in std_logic
fmc_lemo1in_n	in std_logic
fmc_present_n	in STD_LOGIC
trigger_L1a	out std_logic
trigger_Orbit	out std_logic := ' 0 '
trigger_Inhibit	out std_logic := ' 0 '
trigger_BGO	out std_logic := ' 0 '
eeprom_sda	inout STD_Logic
eeprom_scl	out STD_Logic
mpod_sda	inout STD_Logic
mpod_scl	out STD_Logic
bridge_sda	inout STD_Logic
bridge_scl	out STD_Logic
bridge_reset_n	out STD_Logic
adcs_sda	inout STD_Logic
adcs_scl	out STD_Logic

Member Data Documentation

adcs_scl

adcs_scl out STD_Logic

Port

adcs_sda

adcs_sda inout STD_Logic

Port

aerr_led_n

aerr_led_n out std_logic

Port

alert_led_n

alert_led_n out std_logic

Port

bridge_reset_n

bridge_reset_n out STD_Logic

Port

bridge_scl

bridge_scl out STD_Logic

Port

bridge_sda

bridge_sda inout STD_Logic

Port

cdr40M_n

cdr40M_n in std_logic

Port

cdr40M_p

cdr40M_p in std_logic

Port

cdrclk_n

cdrclk_n in std_logic

Port

cdrclk_p

cdrclk_p in std_logic

Port

cdrdata_n

cdrdata_n in std_logic

Port

cdrdata_p

cdrdata_p in std_logic

Port

clk40M_n

clk40M_n in STD_LOGIC

Port

clk40M_p

clk40M_p in STD_LOGIC

Port

config_csn

config_csn out STD_LOGIC

Port

config_miso

config_miso in STD_LOGIC

Port

config_mosi

config_mosi out STD_LOGIC

Port

div_div4

div_div4 out std_logic

Port

div_rstn

div_rstn out std_logic

Port

dss_done

dss_done in std_logic_vector ( 2 downto 1 )

Port

dss_init_b

dss_init_b in std_logic_vector ( 2 downto 1 )

Port

dss_prog_b

dss_prog_b out std_logic_vector ( 2 downto 1 )

Port

dss_reset

dss_reset out std_logic_vector ( 2 downto 1 )

Port

eeprom_scl

eeprom_scl out STD_Logic

Port

eeprom_sda

eeprom_sda inout STD_Logic

Port

flash_clk

flash_clk out STD_LOGIC

Port

flash_csn

flash_csn out STD_LOGIC

Port

flash_miso

flash_miso in STD_LOGIC

Port

flash_mosi

flash_mosi out STD_LOGIC

Port

flash_sel_b

flash_sel_b out std_logic_vector ( 2 downto 1 )

Port

FLAVOUR

FLAVOUR integer := 0

Generic

Integer used to distinguish different FPGAs having a slightly different firmware.

fmc_lemo1in_n

fmc_lemo1in_n in std_logic

Port

fmc_lemo1in_p

fmc_lemo1in_p in std_logic

Port

fmc_present_n

fmc_present_n in STD_LOGIC

Port

force_mac_n

force_mac_n in std_logic

Port

ftm [1/2]

ftm

Library

ftm [2/2]

ftm

Package

FTM_FWHASH

FTM_FWHASH std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Short 7-digit git sha.

FTM_FWVERSION

FTM_FWVERSION std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Version of algolib library (format: MMmmcccc in hex)

ftm_mgt

ftm_mgt

Package

GLOBAL_FWDATE

GLOBAL_FWDATE std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Date format DDMMYYYY in decimal.

GLOBAL_FWHASH

GLOBAL_FWHASH std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Short 7-digit git SHA of the repository.

GLOBAL_FWTIME

GLOBAL_FWTIME std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Time format 00HHMMSS in decimal.

GLOBAL_FWVERSION

GLOBAL_FWVERSION std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Version of the repository (format: MMmmcccc in hex)

gmii_gtx_clk

gmii_gtx_clk out STD_LOGIC

Port

gmii_rx_clk

gmii_rx_clk in STD_LOGIC

Port

gmii_rx_dv

gmii_rx_dv in STD_LOGIC

Port

gmii_rx_er

gmii_rx_er in STD_LOGIC

Port

gmii_rxd

gmii_rxd in STD_LOGIC_VECTOR ( 7 downto 0 )

Port

gmii_tx_en

gmii_tx_en out STD_LOGIC

Port

gmii_tx_er

gmii_tx_er out STD_LOGIC

Port

gmii_txd

gmii_txd out STD_LOGIC_VECTOR ( 7 downto 0 )

Port

HOG_FWHASH

HOG_FWHASH std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Short 7-digit git SHA of the Hog submodule.

hub1_led_n

hub1_led_n out std_logic

Port

hw_addr

hw_addr in std_logic_vector ( 4 downto 0 )

Port

IEEE

IEEE

Library

ipbus

ipbus

Package

IPBUS_LIB_FWHASH

IPBUS_LIB_FWHASH std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Short 7-digit git SHA of the ipbus submodule.

lappio_n

lappio_n in std_logic_vector ( 3 downto 0 )

Port

mac_arbiter_decl

mac_arbiter_decl

Package

master1_rx_data_n

master1_rx_data_n out std_logic_vector ( 8 DOWNTO 0 )

Port

master1_rx_data_p

master1_rx_data_p out std_logic_vector ( 8 DOWNTO 0 )

Port

master1_rx_parity_n

master1_rx_parity_n out std_logic

Port

master1_rx_parity_p

master1_rx_parity_p out std_logic

Port

master1_tx_data_n

master1_tx_data_n in std_logic_vector ( 8 DOWNTO 0 )

Port

master1_tx_data_p

master1_tx_data_p in std_logic_vector ( 8 DOWNTO 0 )

Port

master1_tx_parity_n

master1_tx_parity_n in std_logic

Port

master1_tx_parity_p

master1_tx_parity_p in std_logic

Port

master1_tx_pause_n

master1_tx_pause_n out std_logic

Port

master1_tx_pause_p

master1_tx_pause_p out std_logic

Port

master2_rx_data_n

master2_rx_data_n out std_logic_vector ( 8 DOWNTO 0 )

Port

master2_rx_data_p

master2_rx_data_p out std_logic_vector ( 8 DOWNTO 0 )

Port

master2_rx_parity_n

master2_rx_parity_n out std_logic

Port

master2_rx_parity_p

master2_rx_parity_p out std_logic

Port

master2_tx_data_n

master2_tx_data_n in std_logic_vector ( 8 DOWNTO 0 )

Port

master2_tx_data_p

master2_tx_data_p in std_logic_vector ( 8 DOWNTO 0 )

Port

master2_tx_parity_n

master2_tx_parity_n in std_logic

Port

master2_tx_parity_p

master2_tx_parity_p in std_logic

Port

master2_tx_pause_n

master2_tx_pause_n out std_logic

Port

master2_tx_pause_p

master2_tx_pause_p out std_logic

Port

mpod_scl

mpod_scl out STD_Logic

Port

mpod_sda

mpod_sda inout STD_Logic

Port

node_led_n

node_led_n out std_logic

Port

not_ttc

not_ttc in std_logic

Port

NSRC

NSRC positive := 3

Generic

numeric_std

numeric_std

Package

OFFICIAL

OFFICIAL std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

bit 31 is official, bit 30:16 reserved, bit 15:0 AWE attempt number

pcb_version_n

pcb_version_n in std_logic_vector ( 1 downto 0 )

Port

phy_rstb

phy_rstb out STD_LOGIC

Port

pll_clk

pll_clk out STD_LOGIC

Port

pll_le_b

pll_le_b out std_logic_vector ( 3 downto 0 )

Port

pll_lock

pll_lock in STD_LOGIC_VECTOR ( 3 downto 0 )

Port

pll_miso

pll_miso in STD_LOGIC

Port

pll_mosi

pll_mosi out STD_LOGIC

Port

pll_powerdn_b

pll_powerdn_b out STD_LOGIC

Port

pll_sync_b

pll_sync_b out std_logic_vector ( 3 downto 0 )

Port

Q115_REFCLK1_N

Q115_REFCLK1_N in std_logic

Port

Q115_REFCLK1_P

Q115_REFCLK1_P in std_logic

Port

Q116_REFCLK1_N

Q116_REFCLK1_N in std_logic

Port

Q116_REFCLK1_P

Q116_REFCLK1_P in std_logic

Port

Q117_REFCLK1_N

Q117_REFCLK1_N in std_logic

Port

Q117_REFCLK1_P

Q117_REFCLK1_P in std_logic

Port

Q118_REFCLK1_N

Q118_REFCLK1_N in std_logic

Port

Q118_REFCLK1_P

Q118_REFCLK1_P in std_logic

Port

rot_switch

rot_switch in std_logic_vector ( 3 downto 0 )

Port

run_dss1_n

run_dss1_n out std_logic

Port

run_dss1_p

run_dss1_p out std_logic

Port

run_dss2_n

run_dss2_n out std_logic

Port

run_dss2_p

run_dss2_p out std_logic

Port

RXN_IN_115_116

RXN_IN_115_116 in std_logic_vector ( 7 downto 0 )

Port

RXN_IN_117_118

RXN_IN_117_118 in std_logic_vector ( 7 downto 0 )

Port

RXP_IN_115_116

RXP_IN_115_116 in std_logic_vector ( 7 downto 0 )

Port

RXP_IN_117_118

RXP_IN_117_118 in std_logic_vector ( 7 downto 0 )

Port

spi

spi

Package

STD_LOGIC_1164

STD_LOGIC_1164

Package

sync_dss1_n

sync_dss1_n out std_logic

Port

sync_dss1_p

sync_dss1_p out std_logic

Port

sync_dss2_n

sync_dss2_n out std_logic

Port

sync_dss2_p

sync_dss2_p out std_logic

Port

sysclk_n

sysclk_n in STD_LOGIC

Port

sysclk_p

sysclk_p in STD_LOGIC

Port

TOP_FWHASH

TOP_FWHASH std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Short 7-digit git SHA of the top folder: list files, tcl file.

TOP_FWVERSION

TOP_FWVERSION std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Version of the top folder, see TOP_FWHASH.

trigger_BGO

trigger_BGO out std_logic := ' 0 '

Port

trigger_Inhibit

trigger_Inhibit out std_logic := ' 0 '

Port

trigger_L1a

trigger_L1a out std_logic

Port

trigger_Orbit

trigger_Orbit out std_logic := ' 0 '

Port

ttc_lol

ttc_lol in std_logic

Port

ttc_los

ttc_los in std_logic

Port

ttcfmc_2de

ttcfmc_2de out std_logic

Port

ttcfmc_led

ttcfmc_led out std_logic

Port

TXN_OUT_115_116

TXN_OUT_115_116 out std_logic_vector ( 7 downto 0 )

Port

TXN_OUT_117_118

TXN_OUT_117_118 out std_logic_vector ( 7 downto 0 )

Port

TXP_OUT_115_116

TXP_OUT_115_116 out std_logic_vector ( 7 downto 0 )

Port

TXP_OUT_117_118

TXP_OUT_117_118 out std_logic_vector ( 7 downto 0 )

Port

unisim

unisim

Library

vadj_off

vadj_off out std_logic

Port

VComponents

VComponents

Package

XML_HASH

XML_HASH std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Short 7-digit git SHA of the XMLs.

XML_VERSION

XML_VERSION std_logic_vector ( 31 downto 0 ) := x " 00000000 "

Generic

Version of the XMLs.

---

The documentation for this class was generated from the following file:

• Top/FTM_Control/top_FTM_Control.vhd