rtl Architecture Reference

Processes
PROCESS_949	( ipb_clk )
PROCESS_950	( clk125 )
PROCESS_951	( clk125 )
PROCESS_952	( rst_ipb , ipb_clk )
PROCESS_953	( ShelfNo )
PROCESS_954	( pll_select , pll_csn )

Constants
N_TXS	positive := 16
N_RXS	positive := 16
TIC	positive := 9
HUB1	std_logic_vector ( 4 downto 0 ) := " 00001 "
ip_addr_table	ip_addr_array := ( X " 0A0B1E25 " , X " 0A0B1E26 " , X " 0A0B1E27 " , X " 0A0B1E28 " , X " 0A0B1E29 " , X " 0A0B1E2A " , X " 0A0B1E2B " , X " 0A0B1E2C " , X " 0A0B1E2D " , X " 0A0B1E2E " , others = > X " 0A0B1E25 " )
H_BITS	positive := 18

Types
ip_addr_array	( 0 to 15 ) std_logic_vector ( 31 downto 0 )

Signals
clk125	STD_LOGIC
clk200	STD_LOGIC
ipb_clk	STD_LOGIC
locked	STD_LOGIC
rst_125	STD_LOGIC
rst_ipb	STD_LOGIC
onehz	STD_LOGIC
mac_tx_data	std_logic_vector ( 7 downto 0 )
mac_rx_data	std_logic_vector ( 7 downto 0 )
mac_tx_valid	std_logic
mac_tx_last	std_logic
mac_tx_error	std_logic
mac_tx_ready	std_logic
mac_rx_valid	std_logic
mac_rx_last	std_logic
mac_rx_error	std_logic
ipb_master_out	ipb_wbus
ipb_master_in	ipb_rbus
mac_addr	std_logic_vector ( 47 downto 0 )
ip_addr	std_logic_vector ( 31 downto 0 )
sys_rst	std_logic
ttc_status	std_logic_vector ( 127 downto 0 )
ttc_fmc_lemo	std_logic
ttc_enable	std_logic
ttc_selected	std_logic
run_dss	std_logic
sync_dss	std_logic
flash_o_int	spi_mo
flash_i_int	spi_mi
pll_o_int	spi_mo
pll_i_int	spi_mi
pll_csn	std_logic
flash_select	std_logic_vector ( 1 downto 0 )
pll_select	std_logic_vector ( 1 downto 0 )
toggle_bit	std_logic
vadj_on	std_logic
pll_powerdn	std_logic
pll_sync	std_logic
pll_sync_command	std_logic
pll_sync_reg	std_logic
dss_reprog	std_logic_vector ( 2 downto 1 )
src_tx_data_bus	mac_arbiter_slv_array ( NSRC - 1 downto 0 )
src_tx_valid_bus	mac_arbiter_sl_array ( NSRC - 1 downto 0 )
src_tx_last_bus	mac_arbiter_sl_array ( NSRC - 1 downto 0 )
src_tx_error_bus	mac_arbiter_sl_array ( NSRC - 1 downto 0 )
src_tx_ready_bus	mac_arbiter_sl_array ( NSRC - 1 downto 0 )
Actual_mac_addr	std_logic_vector ( 47 downto 0 )
Actual_ip_addr	std_logic_vector ( 31 downto 0 )
Got_IP_addr	std_logic
Slaves_got_IP_addr	std_logic
rarp_rx_data	std_logic_vector ( 7 DOWNTO 0 )
rarp_rx_last	std_logic
rarp_rx_valid	std_logic
FIFO1_WriteEn	STD_LOGIC
FIFO2_WriteEn	STD_LOGIC
FIFO1_Data	STD_LOGIC_VECTOR ( 9 downto 0 )
FIFO2_Data	STD_LOGIC_VECTOR ( 9 downto 0 )
FIFO1_Full	STD_LOGIC
FIFO2_Full	STD_LOGIC
DSS1_got_IP_addr	STD_LOGIC
DSS2_got_IP_addr	STD_LOGIC
master1_tx_data	std_logic_vector ( 8 DOWNTO 0 )
master1_tx_parity	std_logic
master2_tx_data	std_logic_vector ( 8 DOWNTO 0 )
master2_tx_parity	std_logic
master1_tx_data_reg	std_logic_vector ( 8 DOWNTO 0 )
master1_tx_parity_reg	std_logic
master2_tx_data_reg	std_logic_vector ( 8 DOWNTO 0 )
master2_tx_parity_reg	std_logic
master1_link_down	std_logic
master2_link_down	std_logic
master1_rx_data	std_logic_vector ( 8 DOWNTO 0 )
master1_rx_data_reg	std_logic_vector ( 8 DOWNTO 0 )
master1_rx_parity	std_logic
master1_rx_parity_reg	std_logic
master2_rx_data	std_logic_vector ( 8 DOWNTO 0 )
master2_rx_data_reg	std_logic_vector ( 8 DOWNTO 0 )
master2_rx_parity	std_logic
master2_rx_parity_reg	std_logic
master1_tx_pause	std_logic
master2_tx_pause	std_logic
master1_tx_err	std_logic
master2_tx_err	std_logic
eeprom_sda_o	std_logic
eeprom_sda_i	std_logic
mpod_sda_o	std_logic
mpod_sda_i	std_logic
bridge_sda_o	std_logic
bridge_sda_i	std_logic
bridge_reset	std_logic
adcs_sda_o	std_logic
adcs_sda_i	std_logic
cdrclk_in	std_logic
cdrdata_in	std_logic
cdr40M_in	std_logic
clk40M_in	std_logic
clk40M	std_logic
ipmc_usrio	std_logic_vector ( 3 DOWNTO 0 )
ShelfNo	std_logic_vector ( 3 DOWNTO 0 )
pcb_version	std_logic_vector ( 1 downto 0 )
debug	std_logic
module_serial_number	std_logic_vector ( 7 DOWNTO 0 )
module_sn	integer range 0 to 15
LOGIC_0	std_logic := ' 0 '
LOGIC_1	std_logic := ' 1 '
mgt_loopback	std_logic_vector ( 2 downto 0 ) := " 000 "
mgt_source_data	mgt_data_array ( N_TXS - 1 downto 0 )
mgt_source_clk2	std_logic_vector ( N_TXS - 1 downto 0 )
mgt_sink_data	mgt_data_array ( N_RXS - 1 downto 0 )
mgt_sink_clk2	std_logic_vector ( N_RXS - 1 downto 0 )
mgt_source_data_s	mgt_data_array ( N_TXS - 1 downto 0 )
soft_reset_tx	std_logic := ' 0 '
soft_reset_rx	std_logic := ' 0 '
mgt_tx_reset	std_logic := ' 0 '
mgt_rx_reset	std_logic := ' 0 '
mgt_control_115_116	mgt_2quad_control
mgt_control_117_118	mgt_2quad_control
mgt_status_115_116	mgt_2quad_status
mgt_status_117_118	mgt_2quad_status
mgt_control	mgt_control_bundle
mgt_status	mgt_status_bundle
ttcinfo_data	mgt_data
ttcinfo_clko	std_logic
ttcinfo_sink_data	mgt_data
ttcinfo_sink_clko	std_logic
FTM_L1A	std_logic
use_serial_no	boolean := FALSE
force_ipadd	boolean := FALSE
holdoff_count	unsigned ( H_BITS DOWNTO 0 ) := ( others = > ' 0 ' )
ipbus_enable	std_logic := ' 0 '
ttc_bcrst	std_logic
ttc_ecr	std_logic
ttc_l1a	std_logic

Attributes
PULLUP	string
PULLUP	pcb_version_n : signal is " TRUE "
dont_touch	string
dont_touch	onehz : signal is " true "
PRESERVE_SIGNAL	boolean
PRESERVE_SIGNAL	toggle_bit : signal is true

Instantiations
mgts_115_116	con_2quads_6g4_mgts <Entity con_2quads_6g4_mgts>
mgts_117_118	con_2quads_6g4_mgts <Entity con_2quads_6g4_mgts>
external_pll	pll_synch <Entity pll_synch>
clocks	clocks_7s_extphy <Entity clocks_7s_extphy>
tx_arbiter	mac_arbiter <Entity mac_arbiter>
rarpd	udp_master_rarp <Entity udp_master_rarp>
udp_master_if1	UDP_master_if <Entity UDP_master_if>
udp_fifo1	UDP_master_fifo <Entity UDP_master_fifo>
udp_master_if2	UDP_master_if <Entity UDP_master_if>
udp_fifo2	UDP_master_fifo <Entity UDP_master_fifo>
m2s_1	obufds
m2s_1p	obufds
m2s_2	obufds
m2s_2p	obufds
m2s_1pause	obufds
m2s_2pause	obufds
s2m_1	ibufds
s2m_2	ibufds
s2m_1txe	ibufds
s2m_2txe	ibufds
eth	eth_7s_gmii <Entity eth_7s_gmii>
ipbus	ipbus_ctrl <Entity ipbus_ctrl>
ibufd40mclk	ibufgds
bufg40m	bufg
slaves	slaves <Entity slaves>
cclk_o	startup <Entity startup>
ibufgds0	ibufds
ttc	ttc_fmc <Entity ttc_fmc>
ibufdcdrclk	ibufgds
ibufdfmcclk	ibufgds
ibufddata	ibufgds
dss1run	obufds
dss2run	obufds
dss1sync	obufds
dss2sync	obufds

Member Function Documentation

PROCESS_949()

PROCESS_949

(

ipb_clk

)

PROCESS_950()

PROCESS_950 (   clk125   )

Process

PROCESS_951()

PROCESS_951

(

clk125

)

PROCESS_952()

PROCESS_952	(		rst_ipb,
			ipb_clk
	)

PROCESS_953()

PROCESS_953

(

ShelfNo

)

PROCESS_954()

PROCESS_954	(		pll_select,
			pll_csn
	)

Member Data Documentation

Actual_ip_addr

Actual_ip_addr std_logic_vector ( 31 downto 0 )

Signal

Actual_mac_addr

Actual_mac_addr std_logic_vector ( 47 downto 0 )

Signal

adcs_sda_i

adcs_sda_i std_logic

Signal

adcs_sda_o

adcs_sda_o std_logic

Signal

bridge_reset

bridge_reset std_logic

Signal

bridge_sda_i

bridge_sda_i std_logic

Signal

bridge_sda_o

bridge_sda_o std_logic

Signal

bufg40m

bufg40m bufg

Instantiation

cclk_o

cclk_o startup

Instantiation

cdr40M_in

cdr40M_in std_logic

Signal

cdrclk_in

cdrclk_in std_logic

Signal

cdrdata_in

cdrdata_in std_logic

Signal

clk125

clk125 STD_LOGIC

Signal

clk200

clk200 STD_LOGIC

Signal

clk40M

clk40M std_logic

Signal

clk40M_in

clk40M_in std_logic

Signal

clocks

clocks clocks_7s_extphy

Instantiation

debug

debug std_logic

Signal

dont_touch [1/2]

dont_touch string

Attribute

dont_touch [2/2]

dont_touch onehz : signal is " true "

Attribute

DSS1_got_IP_addr

DSS1_got_IP_addr STD_LOGIC

Signal

dss1run

dss1run obufds

Instantiation

dss1sync

dss1sync obufds

Instantiation

DSS2_got_IP_addr

DSS2_got_IP_addr STD_LOGIC

Signal

dss2run

dss2run obufds

Instantiation

dss2sync

dss2sync obufds

Instantiation

dss_reprog

dss_reprog std_logic_vector ( 2 downto 1 )

Signal

eeprom_sda_i

eeprom_sda_i std_logic

Signal

eeprom_sda_o

eeprom_sda_o std_logic

Signal

eth

eth eth_7s_gmii

Instantiation

external_pll

external_pll pll_synch

Instantiation

FIFO1_Data

FIFO1_Data STD_LOGIC_VECTOR ( 9 downto 0 )

Signal

FIFO1_Full

FIFO1_Full STD_LOGIC

Signal

FIFO1_WriteEn

FIFO1_WriteEn STD_LOGIC

Signal

FIFO2_Data

FIFO2_Data STD_LOGIC_VECTOR ( 9 downto 0 )

Signal

FIFO2_Full

FIFO2_Full STD_LOGIC

Signal

FIFO2_WriteEn

FIFO2_WriteEn STD_LOGIC

Signal

flash_i_int

flash_i_int spi_mi

Signal

flash_o_int

flash_o_int spi_mo

Signal

flash_select

flash_select std_logic_vector ( 1 downto 0 )

Signal

force_ipadd

force_ipadd boolean := FALSE

Signal

FTM_L1A

FTM_L1A std_logic

Signal

Got_IP_addr

Got_IP_addr std_logic

Signal

H_BITS

H_BITS positive := 18

Constant

holdoff_count

holdoff_count unsigned ( H_BITS DOWNTO 0 ) := ( others = > ' 0 ' )

Signal

HUB1

HUB1 std_logic_vector ( 4 downto 0 ) := " 00001 "

Constant

ibufd40mclk

ibufd40mclk ibufgds

Instantiation

ibufdcdrclk

ibufdcdrclk ibufgds

Instantiation

ibufddata

ibufddata ibufgds

Instantiation

ibufdfmcclk

ibufdfmcclk ibufgds

Instantiation

ibufgds0

ibufgds0 ibufds

Instantiation

ip_addr

ip_addr std_logic_vector ( 31 downto 0 )

Signal

ip_addr_array

ip_addr_array ( 0 to 15 ) std_logic_vector ( 31 downto 0 )

Type

ip_addr_table

ip_addr_table ip_addr_array := ( X " 0A0B1E25 " , X " 0A0B1E26 " , X " 0A0B1E27 " , X " 0A0B1E28 " , X " 0A0B1E29 " , X " 0A0B1E2A " , X " 0A0B1E2B " , X " 0A0B1E2C " , X " 0A0B1E2D " , X " 0A0B1E2E " , others = > X " 0A0B1E25 " )

Constant

ipb_clk

ipb_clk STD_LOGIC

Signal

ipb_master_in

ipb_master_in ipb_rbus

Signal

ipb_master_out

ipb_master_out ipb_wbus

Signal

ipbus

ipbus ipbus_ctrl

Instantiation

ipbus_enable

ipbus_enable std_logic := ' 0 '

Signal

ipmc_usrio

ipmc_usrio std_logic_vector ( 3 DOWNTO 0 )

Signal

locked

locked STD_LOGIC

Signal

LOGIC_0

LOGIC_0 std_logic := ' 0 '

Signal

LOGIC_1

LOGIC_1 std_logic := ' 1 '

Signal

m2s_1

m2s_1 obufds

Instantiation

m2s_1p

m2s_1p obufds

Instantiation

m2s_1pause

m2s_1pause obufds

Instantiation

m2s_2

m2s_2 obufds

Instantiation

m2s_2p

m2s_2p obufds

Instantiation

m2s_2pause

m2s_2pause obufds

Instantiation

mac_addr

mac_addr std_logic_vector ( 47 downto 0 )

Signal

mac_rx_data

mac_rx_data std_logic_vector ( 7 downto 0 )

Signal

mac_rx_error

mac_rx_error std_logic

Signal

mac_rx_last

mac_rx_last std_logic

Signal

mac_rx_valid

mac_rx_valid std_logic

Signal

mac_tx_data

mac_tx_data std_logic_vector ( 7 downto 0 )

Signal

mac_tx_error

mac_tx_error std_logic

Signal

mac_tx_last

mac_tx_last std_logic

Signal

mac_tx_ready

mac_tx_ready std_logic

Signal

mac_tx_valid

mac_tx_valid std_logic

Signal

master1_link_down

master1_link_down std_logic

Signal

master1_rx_data

master1_rx_data std_logic_vector ( 8 DOWNTO 0 )

Signal

master1_rx_data_reg

master1_rx_data_reg std_logic_vector ( 8 DOWNTO 0 )

Signal

master1_rx_parity

master1_rx_parity std_logic

Signal

master1_rx_parity_reg

master1_rx_parity_reg std_logic

Signal

master1_tx_data

master1_tx_data std_logic_vector ( 8 DOWNTO 0 )

Signal

master1_tx_data_reg

master1_tx_data_reg std_logic_vector ( 8 DOWNTO 0 )

Signal

master1_tx_err

master1_tx_err std_logic

Signal

master1_tx_parity

master1_tx_parity std_logic

Signal

master1_tx_parity_reg

master1_tx_parity_reg std_logic

Signal

master1_tx_pause

master1_tx_pause std_logic

Signal

master2_link_down

master2_link_down std_logic

Signal

master2_rx_data

master2_rx_data std_logic_vector ( 8 DOWNTO 0 )

Signal

master2_rx_data_reg

master2_rx_data_reg std_logic_vector ( 8 DOWNTO 0 )

Signal

master2_rx_parity

master2_rx_parity std_logic

Signal

master2_rx_parity_reg

master2_rx_parity_reg std_logic

Signal

master2_tx_data

master2_tx_data std_logic_vector ( 8 DOWNTO 0 )

Signal

master2_tx_data_reg

master2_tx_data_reg std_logic_vector ( 8 DOWNTO 0 )

Signal

master2_tx_err

master2_tx_err std_logic

Signal

master2_tx_parity

master2_tx_parity std_logic

Signal

master2_tx_parity_reg

master2_tx_parity_reg std_logic

Signal

master2_tx_pause

master2_tx_pause std_logic

Signal

mgt_control

mgt_control mgt_control_bundle

Signal

mgt_control_115_116

mgt_control_115_116 mgt_2quad_control

Signal

mgt_control_117_118

mgt_control_117_118 mgt_2quad_control

Signal

mgt_loopback

mgt_loopback std_logic_vector ( 2 downto 0 ) := " 000 "

Signal

mgt_rx_reset

mgt_rx_reset std_logic := ' 0 '

Signal

mgt_sink_clk2

mgt_sink_clk2 std_logic_vector ( N_RXS - 1 downto 0 )

Signal

mgt_sink_data

mgt_sink_data mgt_data_array ( N_RXS - 1 downto 0 )

Signal

mgt_source_clk2

mgt_source_clk2 std_logic_vector ( N_TXS - 1 downto 0 )

Signal

mgt_source_data

mgt_source_data mgt_data_array ( N_TXS - 1 downto 0 )

Signal

mgt_source_data_s

mgt_source_data_s mgt_data_array ( N_TXS - 1 downto 0 )

Signal

mgt_status

mgt_status mgt_status_bundle

Signal

mgt_status_115_116

mgt_status_115_116 mgt_2quad_status

Signal

mgt_status_117_118

mgt_status_117_118 mgt_2quad_status

Signal

mgt_tx_reset

mgt_tx_reset std_logic := ' 0 '

Signal

mgts_115_116

mgts_115_116 con_2quads_6g4_mgts

Instantiation

mgts_117_118

mgts_117_118 con_2quads_6g4_mgts

Instantiation

module_serial_number

module_serial_number std_logic_vector ( 7 DOWNTO 0 )

Signal

module_sn

module_sn integer range 0 to 15

Signal

mpod_sda_i

mpod_sda_i std_logic

Signal

mpod_sda_o

mpod_sda_o std_logic

Signal

N_RXS

N_RXS positive := 16

Constant

N_TXS

N_TXS positive := 16

Constant

onehz

onehz STD_LOGIC

Signal

pcb_version

pcb_version std_logic_vector ( 1 downto 0 )

Signal

pll_csn

pll_csn std_logic

Signal

pll_i_int

pll_i_int spi_mi

Signal

pll_o_int

pll_o_int spi_mo

Signal

pll_powerdn

pll_powerdn std_logic

Signal

pll_select

pll_select std_logic_vector ( 1 downto 0 )

Signal

pll_sync

pll_sync std_logic

Signal

pll_sync_command

pll_sync_command std_logic

Signal

pll_sync_reg

pll_sync_reg std_logic

Signal

PRESERVE_SIGNAL [1/2]

PRESERVE_SIGNAL boolean

Attribute

PRESERVE_SIGNAL [2/2]

PRESERVE_SIGNAL toggle_bit : signal is true

Attribute

PULLUP [1/2]

PULLUP string

Attribute

PULLUP [2/2]

PULLUP pcb_version_n : signal is " TRUE "

Attribute

rarp_rx_data

rarp_rx_data std_logic_vector ( 7 DOWNTO 0 )

Signal

rarp_rx_last

rarp_rx_last std_logic

Signal

rarp_rx_valid

rarp_rx_valid std_logic

Signal

rarpd

rarpd udp_master_rarp

Instantiation

rst_125

rst_125 STD_LOGIC

Signal

rst_ipb

rst_ipb STD_LOGIC

Signal

run_dss

run_dss std_logic

Signal

s2m_1

s2m_1 ibufds

Instantiation

s2m_1txe

s2m_1txe ibufds

Instantiation

s2m_2

s2m_2 ibufds

Instantiation

s2m_2txe

s2m_2txe ibufds

Instantiation

ShelfNo

ShelfNo std_logic_vector ( 3 DOWNTO 0 )

Signal

slaves

slaves slaves

Instantiation

Slaves_got_IP_addr

Slaves_got_IP_addr std_logic

Signal

soft_reset_rx

soft_reset_rx std_logic := ' 0 '

Signal

soft_reset_tx

soft_reset_tx std_logic := ' 0 '

Signal

src_tx_data_bus

src_tx_data_bus mac_arbiter_slv_array ( NSRC - 1 downto 0 )

Signal

src_tx_error_bus

src_tx_error_bus mac_arbiter_sl_array ( NSRC - 1 downto 0 )

Signal

src_tx_last_bus

src_tx_last_bus mac_arbiter_sl_array ( NSRC - 1 downto 0 )

Signal

src_tx_ready_bus

src_tx_ready_bus mac_arbiter_sl_array ( NSRC - 1 downto 0 )

Signal

src_tx_valid_bus

src_tx_valid_bus mac_arbiter_sl_array ( NSRC - 1 downto 0 )

Signal

sync_dss

sync_dss std_logic

Signal

sys_rst

sys_rst std_logic

Signal

TIC

TIC positive := 9

Constant

toggle_bit

toggle_bit std_logic

Signal

ttc

ttc ttc_fmc

Instantiation

ttc_bcrst

ttc_bcrst std_logic

Signal

ttc_ecr

ttc_ecr std_logic

Signal

ttc_enable

ttc_enable std_logic

Signal

ttc_fmc_lemo

ttc_fmc_lemo std_logic

Signal

ttc_l1a

ttc_l1a std_logic

Signal

ttc_selected

ttc_selected std_logic

Signal

ttc_status

ttc_status std_logic_vector ( 127 downto 0 )

Signal

ttcinfo_clko

ttcinfo_clko std_logic

Signal

ttcinfo_data

ttcinfo_data mgt_data

Signal

ttcinfo_sink_clko

ttcinfo_sink_clko std_logic

Signal

ttcinfo_sink_data

ttcinfo_sink_data mgt_data

Signal

tx_arbiter

tx_arbiter mac_arbiter

Instantiation

udp_fifo1

udp_fifo1 UDP_master_fifo

Instantiation

udp_fifo2

udp_fifo2 UDP_master_fifo

Instantiation

udp_master_if1

udp_master_if1 UDP_master_if

Instantiation

udp_master_if2

udp_master_if2 UDP_master_if

Instantiation

use_serial_no

use_serial_no boolean := FALSE

Signal

vadj_on

vadj_on std_logic

Signal

---

The documentation for this class was generated from the following file:

• Top/FTM_Control/top_FTM_Control.vhd