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My Project
v0.0.16
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Entities | |
| struct | architecture |
Libraries | |
| ieee | |
| unisim | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_arith | |
| std_logic_unsigned | |
| VComponents | |
| all | |
| ipbus | Package <ipbus> |
Ports | |
| cdrclk_in | in std_logic |
| cdrdata_in | in std_logic |
| ttc_los | in std_logic |
| ttc_lol | in std_logic |
| div_rstn | out std_logic |
| single_bit_error | out std_logic |
| double_bit_error | out std_logic |
| communication_error | out std_logic |
| ttc_l1a | out std_logic |
| brc_strobe | out std_logic |
| add_strobe | out std_logic |
| ttc_bcr | out std_logic |
| ttc_ecr | out std_logic |
| fmc_present_n | in std_logic |
| ttc_fmc_lemo | in std_logic |
| ttc_status | out std_logic_vector ( 127 downto 0 ) := ( others = > ' 0 ' ) |
| cdrclk_out | out std_logic |
| ready | out std_logic |
| ttc_clk_gated | out std_logic |
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1.8.13