struct Architecture Reference

Signals
cdrbad	std_logic
pll_clk	std_logic
pll_locked	std_logic
brc_t2	std_logic_vector ( 1 downto 0 )
brc_d4	std_logic_vector ( 3 downto 0 )
brc_e	std_logic
brc_b	std_logic
add_a14	std_logic_vector ( 13 downto 0 )
add_e	std_logic
add_s8	std_logic_vector ( 7 downto 0 )
add_d8	std_logic_vector ( 7 downto 0 )
l1a_i	std_logic

Instantiations
pll	pll_160MHz <Entity pll_160MHz>
ttc_dec	ttc_decoder_core <Entity ttc_decoder_core>

Member Data Documentation

add_a14

add_a14 std_logic_vector ( 13 downto 0 )

Signal

add_d8

add_d8 std_logic_vector ( 7 downto 0 )

Signal

add_e

add_e std_logic

Signal

add_s8

add_s8 std_logic_vector ( 7 downto 0 )

Signal

brc_b

brc_b std_logic

Signal

brc_d4

brc_d4 std_logic_vector ( 3 downto 0 )

Signal

brc_e

brc_e std_logic

Signal

brc_t2

brc_t2 std_logic_vector ( 1 downto 0 )

Signal

cdrbad

cdrbad std_logic

Signal

l1a_i

l1a_i std_logic

Signal

pll

pll pll_160MHz

Instantiation

pll_clk

pll_clk std_logic

Signal

pll_locked

pll_locked std_logic

Signal

ttc_dec

ttc_dec ttc_decoder_core

Instantiation

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The documentation for this class was generated from the following file:

• common/TTC_FMC/hdl/ipbus_ttc_fmc_wrapper.vhd