My Project  v0.0.16
Ports | Libraries | Use Clauses
transactor_if Entity Reference
Inheritance diagram for transactor_if:
Inheritance graph
[legend]

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
numeric_std 
ipbus_trans_decl  Package <ipbus_trans_decl>

Ports

clk   in std_logic
rst   in std_logic
trans_in   in ipbus_trans_in
trans_out   out ipbus_trans_out
ipb_req   out std_logic
ipb_grant   in std_logic
rx_ready   out std_logic
rx_next   in std_logic
rx_data   out std_logic_vector ( 31 downto 0 )
tx_data   in std_logic_vector ( 31 downto 0 )
tx_we   in std_logic
tx_hdr   in std_logic
tx_err   in std_logic

Member Data Documentation

◆ clk

clk in std_logic
Port

◆ ieee

ieee
Library

◆ ipb_grant

ipb_grant in std_logic
Port

◆ ipb_req

ipb_req out std_logic
Port

◆ ipbus_trans_decl

◆ numeric_std

numeric_std
Package

◆ rst

rst in std_logic
Port

◆ rx_data

rx_data out std_logic_vector ( 31 downto 0 )
Port

◆ rx_next

rx_next in std_logic
Port

◆ rx_ready

rx_ready out std_logic
Port

◆ std_logic_1164

std_logic_1164
Package

◆ trans_in

◆ trans_out

◆ tx_data

tx_data in std_logic_vector ( 31 downto 0 )
Port

◆ tx_err

tx_err in std_logic
Port

◆ tx_hdr

tx_hdr in std_logic
Port

◆ tx_we

tx_we in std_logic
Port

The documentation for this class was generated from the following file: