rtl Architecture Reference

Processes
PROCESS_43	( clk )
PROCESS_44	( clk )
PROCESS_45	( clk )
PROCESS_58	( clk )
PROCESS_59	( clk )
PROCESS_60	( clk )
PROCESS_595	( clk )
PROCESS_596	( clk )
PROCESS_597	( clk )

Types
state_type	( ST_IDLE , ST_FIRST , ST_HDR , ST_PREBODY , ST_BODY , ST_DONE , ST_GAP )

Signals
state	state_type
dinit	std_logic
dinit_d	std_logic
dnext	std_logic
dnext_d	std_logic
dsel	std_logic
rxd	std_logic_vector ( 31 downto 0 )
rxf	std_logic_vector ( 31 downto 0 )
raddr	unsigned ( addr_width - 1 downto 0 )
waddr	unsigned ( addr_width - 1 downto 0 )
haddr	unsigned ( addr_width - 1 downto 0 )
waddrh	unsigned ( addr_width - 1 downto 0 )
hlen	unsigned ( 15 downto 0 )
blen	unsigned ( 15 downto 0 )
rctr	unsigned ( 15 downto 0 )
wctr	unsigned ( 15 downto 0 )
idata	std_logic_vector ( 31 downto 0 )
rdata	std_logic_vector ( 31 downto 0 )
first	std_logic
start	std_logic
start_d	std_logic

Member Function Documentation

PROCESS_43()

PROCESS_43 (   clk   )

Process

PROCESS_44()

PROCESS_44 (   clk   )

Process

PROCESS_45()

PROCESS_45 (   clk   )

Process

PROCESS_58()

PROCESS_58 (   clk   )

Process

PROCESS_59()

PROCESS_59 (   clk   )

Process

PROCESS_595()

PROCESS_595 (   clk   )

Process

PROCESS_596()

PROCESS_596 (   clk   )

Process

PROCESS_597()

PROCESS_597 (   clk   )

Process

PROCESS_60()

PROCESS_60 (   clk   )

Process

Member Data Documentation

blen

blen unsigned ( 15 downto 0 )

Signal

dinit

dinit std_logic

Signal

dinit_d

dinit_d std_logic

Signal

dnext

dnext std_logic

Signal

dnext_d

dnext_d std_logic

Signal

dsel

dsel std_logic

Signal

first

first std_logic

Signal

haddr

haddr unsigned ( addr_width - 1 downto 0 )

Signal

hlen

hlen unsigned ( 15 downto 0 )

Signal

idata

idata std_logic_vector ( 31 downto 0 )

Signal

raddr

raddr unsigned ( addr_width - 1 downto 0 )

Signal

rctr

rctr unsigned ( 15 downto 0 )

Signal

rdata

rdata std_logic_vector ( 31 downto 0 )

Signal

rxd

rxd std_logic_vector ( 31 downto 0 )

Signal

rxf

rxf std_logic_vector ( 31 downto 0 )

Signal

start

start std_logic

Signal

start_d

start_d std_logic

Signal

state

state state_type

Signal

state_type

state_type ( ST_IDLE , ST_FIRST , ST_HDR , ST_PREBODY , ST_BODY , ST_DONE , ST_GAP )

Type

waddr

waddr unsigned ( addr_width - 1 downto 0 )

Signal

waddrh

waddrh unsigned ( addr_width - 1 downto 0 )

Signal

wctr

wctr unsigned ( 15 downto 0 )

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_core/firmware/hdl/transactor_if.vhd